EP1810LC-20T vs EP1810LC-25T Ikinahambing
Detalyadong pagkakahiwalay na pagkakahambing ng EP1810LC-20T sa pamamagitan ng Intel at EP1810LC-25T sa pamamagitan ng Intel. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.
Pagsanggunian na paghahambing
| Parametro | EP1810LC-20T | EP1810LC-25T |
|---|---|---|
| Brand | Intel | Intel |
| Kategorya | FPGA & CPLD | FPGA & CPLD |
| Katayuan ng Lifecycle | Obsolete | NRND |
| Family | Altera Classic EPLD | Altera Classic EP1810 |
| Product Type | CPLD (Complex Programmable Logic Device) | — |
| Usable Gates | 900 gates | Approx. 900 |
| Macrocells | 48 | 48 (4 quadrants x 12 macrocells) |
| Logic Array Blocks (LABs) | 4 x 12 macrocells | — |
| Maximum Toggle Frequency | 50 MHz | — |
| Pin-to-Pin Logic Delay (tPD) | 20 ns | — |
| Supply Voltage (VCC) | 5 V | 5 V nominal |
| Package Type | PLCC-68 (J-lead) | — |
| Uri ng Pagpapasok | Surface Mount (socket-compatible) | Surface Mount |
| Configuration Memory | On-chip EEPROM (non-volatile) | — |
| Programming Interface | JTAG (IEEE 1149.1) and Altera Master/Slave serial | — |
| Temperature na Operasyon | 0C to +70C (commercial) | 0 °C to +70 °C (commercial) |
| Shipping Format | Tape & Reel ("T" suffix) | — |
| Tindminan RoHS | Non-compliant (legacy 5V PLCC) | [DATA_NEEDED: RoHS status - confirm with manufacturer] |
| Device Type | — | EPLD (Erasable/OTP Complex PLD) |
| Dedicated Inputs | — | 16 |
| Bidirectional I/O Pins | — | 48 |
| External Clocks | — | 4 |
| Propagation Delay (tPD) | — | 25 ns |
| Packhaging | — | 28-pin J-lead PLCC (Plastic Leaded Chip Carrier) |
| Technology | — | CMOS, UV-erasable / OTP |
| I/O Standard | — | TTL-compatible 5 V |
| Programming Tool | — | Altera MAX+PLUS II / Quartus Classic |