EP1810LC-25 vs EP1810LC-20 Ikinahambing
Detalyadong pagkakahiwalay na pagkakahambing ng EP1810LC-25 sa pamamagitan ng Altera at EP1810LC-20 sa pamamagitan ng Intel. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.
Pagsanggunian na paghahambing
| Parametro | EP1810LC-25 | EP1810LC-20 |
|---|---|---|
| Brand | Altera | Intel |
| Kategorya | FPGA & CPLD | FPGA & CPLD |
| Katayuan ng Lifecycle | Obsolete | Obsolete |
| Product Family | Altera Classic EPLD | — |
| Part Number | EP1810LC-25 | — |
| Macrocells | 48 | 48 |
| Propagation Delay (tPD) | 25 ns | 20 ns |
| Dedicated Inputs | 12 | 12 |
| I/O Pins | 48 | — |
| External Clock Inputs | 4 | — |
| Supply Voltage (VCC) | 5 V (TTL-compatible) | — |
| Operating Mode | Turbo-only (no slow-power mode) | — |
| Packhaging | 68-pin JLCC (J-leaded ceramic chip carrier) | 68-pin PLCC |
| Package Code | LC = 68-pin JLCC | — |
| Uri ng Pagpapasok | Surface Mount | Surface Mount |
| Technology | CMOS EPLD (erasable programmable logic device) | CMOS EPROM |
| Programmable Interconnect | Global + Local buses | — |
| Programming Method | Altera Classic programmer + MAX+PLUS II legacy flow | — |
| Katayuan ng Lifecycle | Obsolete (legacy Altera Classic family) | — |
| Tindminan RoHS | [DATA_NEEDED: RoHS compliance not confirmed in legacy datasheet] | [DATA_NEEDED: rohs status] |
| Temperature na Operasyon | [DATA_NEEDED: temperature grade for LC package] | 0C to +70C (commercial) |
| Family | — | Classic EPLD |
| Device Type | — | EPLD (Erasable Programmable Logic Device) |
| Usable Gates | — | 900 |
| Maximum Operating Frequency | — | 50 MHz |
| Volte ng Pagbibigay | — | 5 V (4.75 V to 5.25 V) |
| Programmability | — | UV-Erasable / OTP |
| Package Suffix | — | LC (PLCC, windowed for UV erase on L variant) |
| Speed Grade | — | 20 ns (commercial) |