EP1810LC-35 vs EP1810LC-30 Ikinahambing
Detalyadong pagkakahiwalay na pagkakahambing ng EP1810LC-35 sa pamamagitan ng Rochester Electronics at EP1810LC-30 sa pamamagitan ng Altera. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.
Rochester Electronics
EP1810LC-35 - 48-Macrocell Classic EPLD, 35ns, PLCC-68 | Rochester/Altera
EP1810LC-35 ⚠ Huling Pagbili
Pagsanggunian na paghahambing
| Parametro | EP1810LC-35 | EP1810LC-30 |
|---|---|---|
| Brand | Rochester Electronics | Altera |
| Kategorya | FPGA & CPLD | FPGA & CPLD |
| Katayuan ng Lifecycle | Huling Pagbili | Obsolete |
| Device Type | EPLD (Erasable Programmable Logic Device) | — |
| Series | Classic EP1810 | — |
| Macrocells | 48 | 48 |
| Equivalent Gates | 900 usable / 2100 equivalent | — |
| Maximum Operating Frequency | 28.6 MHz | — |
| Propagation Delay (tpd) | 35 ns (max, '-35' speed grade) | — |
| Supply Voltage (VCC) | 5 V (4.75 V to 5.25 V) | — |
| Technology | CMOS, UV-erasable EPROM | CMOS, low-power (LC) |
| Packhaging | 68-pin PLCC (J-Lead) | JLCC-68 (68-pin J-Lead ceramic chip carrier) |
| Uri ng Pagpapasok | Surface Mount (socketable) | — |
| Temperature na Operasyon | 0C to +70C (commercial) | [DATA_NEEDED: temperature grade] |
| I/O Pins | [DATA_NEEDED: I/O count exact] | — |
| Configuration Method | UV-erase + EPROM programmer | — |
| Programmable Interconnect | Centralized Programmable Interconnect Array (PIA) | — |
| Development Tool (legacy) | MAX+PLUS II / A+PLUS | — |
| Tindminan RoHS | [DATA_NEEDED] | unknown (legacy ceramic package) |
| Lead-Free | [DATA_NEEDED] | — |
| Product Type | — | Classic EPLD (Erasable Programmable Logic Device) |
| Family | — | Altera Classic EPLD |
| Flip-Flops | — | 48 (one per macrocell) |
| Speed Grade (tPD) | — | 30 ns |
| Volte ng Pagbibigay | — | 5 V (typical) |
| Programming | — | Device programmer or JTAG |
| Standby Current | — | [DATA_NEEDED: ICC standby] |
| Bilang ng Pins | — | 68 |
| Number of I/O Pins | — | [DATA_NEEDED: I/O count] |
| Logic Blocks | — | 48 macrocells |