EP1810LI-25 vs EP1810LC-25T Ikinahambing
Detalyadong pagkakahiwalay na pagkakahambing ng EP1810LI-25 sa pamamagitan ng Altera at EP1810LC-25T sa pamamagitan ng Intel. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.
Pagsanggunian na paghahambing
| Parametro | EP1810LI-25 | EP1810LC-25T |
|---|---|---|
| Brand | Altera | Intel |
| Kategorya | FPGA & CPLD | FPGA & CPLD |
| Katayuan ng Lifecycle | Obsolete | NRND |
| Family | Altera Classic EPLD | Altera Classic EP1810 |
| Device Type | EPLD (Erasable Programmable Logic Device), UV-erasable / OTP | EPLD (Erasable/OTP Complex PLD) |
| Macrocells | 48 | 48 (4 quadrants x 12 macrocells) |
| Usable Gates | 900 | Approx. 900 |
| Propagation Delay (tPD) | 25 ns | 25 ns |
| Maximum Counter Frequency | 40 MHz | — |
| Supply Voltage (VCC) | 4.5 V to 5.5 V (nominal 5 V) | 5 V nominal |
| I/O Pins | 48 | — |
| Dedicated Inputs | 12 | 16 |
| Global Clock Inputs | 4 | — |
| Interconnect | Programmable global and local buses | — |
| Packhaging | 68-pin PLCC (J68, J-Lead) | 28-pin J-lead PLCC (Plastic Leaded Chip Carrier) |
| JESD-30 Package Code | S-PQCC-J68 | — |
| Process Technology | CMOS | — |
| Operating Temperature (Industrial 'I' suffix) | -40 C to +85 C | — |
| Programming Mode | EPROM/UV-erasable (windowed) and OTP | — |
| Development Tool | Altera MAX+PLUS II | — |
| Tindminan RoHS | unknown | [DATA_NEEDED: RoHS status - confirm with manufacturer] |
| Lead-Free Status | unknown | — |
| Bidirectional I/O Pins | — | 48 |
| External Clocks | — | 4 |
| Temperature na Operasyon | — | 0 °C to +70 °C (commercial) |
| Uri ng Pagpapasok | — | Surface Mount |
| Technology | — | CMOS, UV-erasable / OTP |
| I/O Standard | — | TTL-compatible 5 V |
| Programming Tool | — | Altera MAX+PLUS II / Quartus Classic |