EP1C20F400C7N vs EP1C20F40017 Ikinahambing
Detalyadong pagkakahiwalay na pagkakahambing ng EP1C20F400C7N sa pamamagitan ng Altera at EP1C20F40017 sa pamamagitan ng Intel. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.
Pagsanggunian na paghahambing
| Parametro | EP1C20F400C7N | EP1C20F40017 |
|---|---|---|
| Brand | Altera | Intel |
| Kategorya | FPGA & CPLD | FPGA & CPLD |
| Katayuan ng Lifecycle | NRND | Obsolete |
| Series | Cyclone | — |
| Family | Cyclone I | Cyclone |
| Logic Elements (LE) | 20,060 | — |
| Logic Array Blocks (LABs) | 2,006 | — |
| Embedded Memory (bits) | 294,912 (288 Kbits, M4K blocks) | 294,912 |
| User I/O Count | 301 | — |
| Embedded 18x18 Multipliers | 52 | — |
| PLLs | 4 | 2 |
| Process Technology | 130 nm CMOS (SRAM-based) | 0.13 µm SRAM |
| Core Voltage | 1.5 V | — |
| Speed Grade | -7 (commercial, ~405 MHz internal) | -17 |
| Temperature na Operasyon | 0 °C to +85 °C (commercial) | 0 °C to +85 °C (commercial) |
| Packhaging | 400-ball FineLine BGA (FBGA) | FBGA-400 (FineLine BGA) |
| Uri ng Pagpapasok | Surface Mount | Surface Mount (BGA) |
| Configuration Interface | Active Serial (AS) / Passive Serial (PS) / JTAG | — |
| I/O Standards Supported | LVTTL, LVCMOS, SSTL, HSTL, LVDS (via 8 I/O banks) | — |
| External Memory Support | DDR SDRAM, QDR SRAM, FCRAM | — |
| Tindminan RoHS | Compliant (per Altera product page) | — |
| Logic Elements | — | 20,060 |
| M4K RAM Blocks | — | 64 |
| Maximum User I/O Pins | — | 301 |
| Core Voltage (VCCINT) | — | 1.5 V |
| I/O Voltage Standards | — | LVTTL, LVCMOS, SSTL, HSTL, LVDS |
| Ball Pitch | — | 0.8 mm |
| Configuration Method | — | Serial (AS mode) or JTAG |