EP1M120B484C5 vs EP1M120B484C8A Ikinahambing
Detalyadong pagkakahiwalay na pagkakahambing ng EP1M120B484C5 sa pamamagitan ng Intel at EP1M120B484C8A sa pamamagitan ng Altera. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.
Pagsanggunian na paghahambing
| Parametro | EP1M120B484C5 | EP1M120B484C8A |
|---|---|---|
| Brand | Intel | Altera |
| Kategorya | FPGA & CPLD | FPGA & CPLD |
| Katayuan ng Lifecycle | NRND | Obsolete |
| Family | Mercury (EP1M) | Mercury (EP1M) |
| Logic Elements | 4,800 | — |
| Typical Gates | 120,000 | — |
| Maximum User I/O | 303 | [DATA_NEEDED: user I/O count] |
| Packhaging | FineLine BGA-484 (19 mm x 19 mm, 1.0 mm pitch) | 484-ball FineLine BGA |
| Temperature na Operasyon | 0C to +85C (commercial) | [DATA_NEEDED: full range] |
| Speed Grade | 5 (slowest) | 8 |
| Core Voltage | 1.8 V | — |
| Process Technology | 0.18 um CMOS | — |
| PLLs | 4 | — |
| Embedded RAM Bits | 49,152 | — |
| True LVDS Channels | Up to 34 pairs | — |
| Maximum LVDS Data Rate | 840 Mbps per channel | — |
| Configuration Scheme | Passive serial, passive parallel synchronous, passive parallel asynchronous, JTAG | — |
| Peak Reflow Temperature | 220 C | 220 C (per JEDEC J-STD-020) |
| Lead-Free / RoHS | SnPb ball finish (non-RoHS by default) | — |
| Multipliers | Embedded in system blocks for DSP | — |
| Uri ng Pagpapasok | Surface Mount | Surface Mount (BGA) |
| Logic Elements (approx.) | — | 120 |
| Bilang ng Pin | — | 484 |
| Temperature Grade | — | Commercial (C) |
| Logic Blocks | — | [DATA_NEEDED: LAB count] |
| Embedded Memory | — | [DATA_NEEDED: RAM bits] |
| Supply Voltage Core | — | [DATA_NEEDED: VCCINT] |
| Supply Voltage I/O | — | [DATA_NEEDED: VCCIO] |
| Configuration Method | — | [DATA_NEEDED: SRAM/serial/etc.] |
| Tindminan RoHS | — | [DATA_NEEDED: check distributor] |
| Level ng MSL | — | [DATA_NEEDED: per JEDEC J-STD-020] |