EP1M120F484C7AES vs EP1M120F484C6N Ikinahambing
Detalyadong pagkakahiwalay na pagkakahambing ng EP1M120F484C7AES sa pamamagitan ng Altera at EP1M120F484C6N sa pamamagitan ng Intel. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.
Pagsanggunian na paghahambing
| Parametro | EP1M120F484C7AES | EP1M120F484C6N |
|---|---|---|
| Brand | Altera | Intel |
| Kategorya | FPGA & CPLD | FPGA & CPLD |
| Katayuan ng Lifecycle | Obsolete | Obsolete |
| Series | Mercury (EP1M120) | — |
| Logic Family | CMOS | — |
| Device Type | FPGA (Field Programmable Gate Array) | — |
| Logic Elements / Cells | 49,152 | — |
| Memory Bits | 4,800 | — |
| User I/O Pins | 303 | — |
| Total Package Pins | 484 | — |
| Package Type | FineLine BGA-484 (PBGA484) | — |
| Terminal Pitch | 1.00 mm | — |
| Supply Voltage (Core) | 1.8 V | — |
| Temperature na Operasyon | 0 C to +85 C | 0C to 85C (commercial) |
| Uri ng Pagpapasok | Surface Mount | Surface Mount |
| Integrated Transceivers | Yes, with CDR up to 1.25 Gbps | — |
| Configuration Method | SRAM (volatile, requires external PROM) | — |
| Tindminan RoHS | unknown | Compliant |
| Family | — | Mercury (APEX PLD platform) |
| Typical Gates | — | 120,000 |
| Logic Cells / Elements | — | 4,800 |
| Logic Array Blocks (LABs) | — | 480 |
| User I/Os | — | 303 |
| Packhaging | — | 484-ball FC-FBGA (FineLine BGA) |
| Core Supply Voltage (VCCINT) | — | 1.71 V to 1.89 V (1.8 V nominal) |
| Transceiver Data Rate | — | Up to 1.25 Gbps with CDR |
| Process Technology | — | CMOS |
| Architecture | — | LUT-based, optimized for high-speed interconnect |
| MultiCore Support | — | Yes (hot socketing) |
| Level ng MSL | — | 3 (per JEDEC J-STD-020) |