EP1M120F484C7AES vs EP1M120F484C6N 比較
詳細並排比較 EP1M120F484C7AES 由 Altera 與 EP1M120F484C6N 由 Intel. 比較關鍵規格、電氣參數、封裝、生命週期狀態、價格與供貨情況，以找出最符合您設計需求的元件。
規格比較
| 參數 | EP1M120F484C7AES | EP1M120F484C6N |
|---|---|---|
| 品牌 | Altera | Intel |
| 類別 | FPGA & CPLD | FPGA & CPLD |
| 生命週期狀態 | Obsolete | Obsolete |
| Series | Mercury (EP1M120) | — |
| Logic Family | CMOS | — |
| Device Type | FPGA (Field Programmable Gate Array) | — |
| Logic Elements / Cells | 49,152 | — |
| Memory Bits | 4,800 | — |
| User I/O Pins | 303 | — |
| Total Package Pins | 484 | — |
| Package Type | FineLine BGA-484 (PBGA484) | — |
| Terminal Pitch | 1.00 mm | — |
| Supply Voltage (Core) | 1.8 V | — |
| 工作溫度 | 0 C to +85 C | 0C to 85C (commercial) |
| 安裝類型 | Surface Mount | Surface Mount |
| Integrated Transceivers | Yes, with CDR up to 1.25 Gbps | — |
| Configuration Method | SRAM (volatile, requires external PROM) | — |
| RoHS 狀態 | unknown | Compliant |
| Family | — | Mercury (APEX PLD platform) |
| Typical Gates | — | 120,000 |
| Logic Cells / Elements | — | 4,800 |
| Logic Array Blocks (LABs) | — | 480 |
| User I/Os | — | 303 |
| 封裝 | — | 484-ball FC-FBGA (FineLine BGA) |
| Core Supply Voltage (VCCINT) | — | 1.71 V to 1.89 V (1.8 V nominal) |
| Transceiver Data Rate | — | Up to 1.25 Gbps with CDR |
| Process Technology | — | CMOS |
| Architecture | — | LUT-based, optimized for high-speed interconnect |
| MultiCore Support | — | Yes (hot socketing) |
| MSL 等級 | — | 3 (per JEDEC J-STD-020) |