EP1M350F780C7ES vs EP1M350F780C8 Ikinahambing
Detalyadong pagkakahiwalay na pagkakahambing ng EP1M350F780C7ES sa pamamagitan ng Intel at EP1M350F780C8 sa pamamagitan ng Altera. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.
Pagsanggunian na paghahambing
| Parametro | EP1M350F780C7ES | EP1M350F780C8 |
|---|---|---|
| Brand | Intel | Altera |
| Kategorya | FPGA & CPLD | FPGA & CPLD |
| Katayuan ng Lifecycle | Aktibo | Obsolete |
| Product Type | Field Programmable Gate Array (FPGA) | — |
| Logic Family | CMOS | — |
| User I/O Count | 486 pins | — |
| Total Package Pins | 780 pins | — |
| Package Type | FINE LINE BGA-780 | — |
| Package Category | 780-BBGA | — |
| Volte ng Pagbibigay | 1.8 V | — |
| Maximum Stated Transceiver Data Rate | 1.25 Gbps | — |
| Channels Supported at 1.25 Gbps | 8 channels | — |
| Remaining Channel Limit | 10 channels at 1.0 Gbps or less | — |
| Temperature na Operasyon | 0 C to 85 C | 0C to +85C (commercial) |
| Clock Data Recovery | Supported | — |
| High-Speed Transceivers | Integrated | — |
| Uri ng Pagpapasok | Surface Mount | Surface Mount (BGA) |
| Tindminan RoHS | unknown | unknown (legacy device) |
| REACH Status | unknown | — |
| Logic Element Count | [DATA_NEEDED: logic element count] | — |
| Embedded Memory Capacity | [DATA_NEEDED: embedded memory capacity] | — |
| Transceiver Count | [DATA_NEEDED: transceiver count] | — |
| Package Dimensions | [DATA_NEEDED: package dimensions] | — |
| Thermal Resistance | [DATA_NEEDED: junction-to-ambient thermal resistance] | — |
| Device Family | — | Altera APEX Mercury (EP1M) |
| Typical Gates | — | 350,000 |
| Maximum Logic Elements (LEs) | — | 12,160 |
| Embedded RAM Blocks | — | 4 dual-port RAM blocks |
| Packhaging | — | 780-ball FineLine BGA |
| Speed Grade | — | C8 (commercial, speed bin 8) |
| Supply Voltage (Core) | — | [DATA_NEEDED: core Vcc] |
| I/O Standards Supported | — | LVTTL, LVCMOS, PCI, SSTL, LVDS (up to 20 standards) |
| Global Clock Networks | — | 8 |
| Configuration Interface | — | IEEE 1532 / passive serial / JTAG |
| Maximum User I/O | — | [DATA_NEEDED: user I/O count] |
| In-System Programmability | — | Yes (ISP via JTAG) |
| Level ng MSL | — | [DATA_NEEDED: MSL rating] |