EP1M350F780I6 vs EP1M350F780I5 Ikinahambing
Detalyadong pagkakahiwalay na pagkakahambing ng EP1M350F780I6 sa pamamagitan ng Altera at EP1M350F780I5 sa pamamagitan ng Altera. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.
Altera
EP1M350F780I5 - Altera Mercury Enhanced Configuration Device, 780-pin FBGA | Intel
EP1M350F780I5 NrndPagsanggunian na paghahambing
| Parametro | EP1M350F780I6 | EP1M350F780I5 |
|---|---|---|
| Brand | Altera | Altera |
| Kategorya | FPGA & CPLD | FPGA & CPLD |
| Katayuan ng Lifecycle | Aktibo | NRND |
| Family | Mercury (PLD) | — |
| Logic Cells | 14,400 | — |
| Equivalent Gates | 350,000 | — |
| User I/Os | 486 | — |
| Embedded Memory (bits) | 114,688 | — |
| Core Supply Voltage | 1.8 V | — |
| Packhaging | 780-ball FC-FBGA (Fine-line) | 780-ball FineLine BGA (F780) |
| Temperature na Operasyon | 0 C to 85 C (Industrial) | — |
| Process Technology | CMOS | — |
| Multi-Gigabit Transceivers | Up to 1.25 Gbps with embedded CDR | — |
| Configuration | JTAG (IEEE 1149.1) / Active Serial (EPC) | — |
| LAB Count | 1,440 (per Mouser listing) | — |
| Uri ng Pagpapasok | Surface Mount | — |
| Level ng MSL | [DATA_NEEDED: MSL rating] | — |
| Tindminan RoHS | [DATA_NEEDED: RoHS status] | [DATA_NEEDED: RoHS status] |
| Device Family | — | Altera Mercury (EP1M) Enhanced Configuration Device |
| Fungsi | — | FPGA configuration PROM with integrated controller |
| Storage Density Code | — | 350 (high-density) |
| Supported Configuration Schemes | — | Passive Serial, Active Serial, Fast Passive Parallel |
| Internal Architecture | — | Configuration controller + flash memory array |
| Programming Method | — | In-system programmable via Altera Quartus / JTAG |
| Temperature Grade (suffix "I") | — | Industrial |
| Speed Grade | — | 5 |
| Target FPGA Compatibility | — | Altera APEX 20K, APEX II, Mercury, Stratix-class high-density FPGAs |
| JTAG Support | — | Yes (IEEE 1149.1 boundary scan) |
| Cascade / Multi-FPGA Support | — | Yes, supports daisy-chained multi-FPGA boot |
| Read-Back | — | Yes |
| Lead-Free | — | [DATA_NEEDED: lead-free status] |