EP1S20B672C6 vs EP1S20F672C6 Ikinahambing
Detalyadong pagkakahiwalay na pagkakahambing ng EP1S20B672C6 sa pamamagitan ng Intel at EP1S20F672C6 sa pamamagitan ng Altera. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.
Pagsanggunian na paghahambing
| Parametro | EP1S20B672C6 | EP1S20F672C6 |
|---|---|---|
| Brand | Intel | Altera |
| Kategorya | FPGA & CPLD | FPGA & CPLD |
| Katayuan ng Lifecycle | Huling Pagbili | Obsolete |
| Family | Stratix | Stratix (first generation) |
| Manufacturer | Intel (formerly Altera) | Altera (now Intel) |
| Logic Elements | 18,460 | — |
| Embedded Memory Bits | 1,669,248 | 1,669,248 |
| User I/O Count | 426 | — |
| Packhaging | 672-ball FineLine BGA (672-BBGA) | 672-ball FineLine BGA |
| Package Dimensions | 35 mm x 35 mm | — |
| Ball Pitch | 1.27 mm | — |
| Process Technology | 130 nm CMOS | 0.13 µm CMOS |
| Core Supply Voltage (VCCINT) | 1.5 V | — |
| I/O Supply Voltage (VCCIO) | 1.5 V / 1.8 V / 2.5 V / 3.3 V | — |
| Speed Grade | C6 | C6 |
| Temperature na Operasyon | 0 C to 85 C (commercial) | 0°C to +85°C (Commercial) |
| Maximum Internal Frequency | 450.05 MHz | — |
| Logic Family | CMOS | — |
| Configuration Method | PS / PPS / PPA / JTAG | — |
| Tindminan RoHS | [DATA_NEEDED: rohs status] | [DATA_NEEDED: RoHS compliance status] |
| Series | — | Stratix |
| Logic Elements (LEs) | — | 18,460 |
| Logic Array Blocks (LABs) | — | 1,846 |
| Maximum User I/Os | — | 426 |
| Package Code | — | F672 |
| Volte ng Pagbibigay | — | Core 1.5 V, I/O programmable |
| Uri ng Pagpapasok | — | Surface Mount |