EP1S20F672C6 vs EP1S20F672I7 Ikinahambing
Detalyadong pagkakahiwalay na pagkakahambing ng EP1S20F672C6 sa pamamagitan ng Altera at EP1S20F672I7 sa pamamagitan ng Intel. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.
Intel
EP1S20F672I7 - Stratix FPGA, 18,460 LEs, 672-BGA | Intel / Altera
EP1S20F672I7 ⚠ Huling PagbiliPagsanggunian na paghahambing
| Parametro | EP1S20F672C6 | EP1S20F672I7 |
|---|---|---|
| Brand | Altera | Intel |
| Kategorya | FPGA & CPLD | FPGA & CPLD |
| Katayuan ng Lifecycle | Obsolete | Huling Pagbili |
| Manufacturer | Altera (now Intel) | — |
| Series | Stratix | — |
| Family | Stratix (first generation) | Stratix (first generation) |
| Process Technology | 0.13 µm CMOS | — |
| Logic Elements (LEs) | 18,460 | 18,460 |
| Logic Array Blocks (LABs) | 1,846 | — |
| Embedded Memory Bits | 1,669,248 | — |
| Maximum User I/Os | 426 | 426 |
| Packhaging | 672-ball FineLine BGA | 672-BBGA (FineLine BGA), 35 x 35 mm, 1.27 mm pitch |
| Package Code | F672 | — |
| Speed Grade | C6 | — |
| Temperature na Operasyon | 0°C to +85°C (Commercial) | -40C to +85C (industrial grade, I7 suffix) |
| Volte ng Pagbibigay | Core 1.5 V, I/O programmable | — |
| Uri ng Pagpapasok | Surface Mount | Surface Mount (BGA) |
| Tindminan RoHS | [DATA_NEEDED: RoHS compliance status] | unknown |
| Maximum RAM Bits | — | 1,669,248 |
| DSP Blocks | — | [DATA_NEEDED: exact DSP block count] |
| Supply Voltage (VCCINT core) | — | 1.5 V |
| Logic Family | — | CMOS |
| Configuration Modes | — | Passive Serial, Passive Parallel, JTAG |
| Number of Pins / Balls | — | 672 |
| Clock Management PLLs | — | [DATA_NEEDED: PLL count] |
| Lead-Free / Finish | — | SnPb (e0 per Partstack datasheet extract) |
| Level ng MSL | — | unknown |
| Status | — | Last Time Buy (per distributor notices) |