EP1S20F672C6 vs EP1S20F672I7 比較
詳細並排比較 EP1S20F672C6 由 Altera 與 EP1S20F672I7 由 Intel. 比較關鍵規格、電氣參數、封裝、生命週期狀態、價格與供貨情況，以找出最符合您設計需求的元件。
規格比較
| 參數 | EP1S20F672C6 | EP1S20F672I7 |
|---|---|---|
| 品牌 | Altera | Intel |
| 類別 | FPGA & CPLD | FPGA & CPLD |
| 生命週期狀態 | Obsolete | 最後購買 |
| Manufacturer | Altera (now Intel) | — |
| Series | Stratix | — |
| Family | Stratix (first generation) | Stratix (first generation) |
| Process Technology | 0.13 µm CMOS | — |
| Logic Elements (LEs) | 18,460 | 18,460 |
| Logic Array Blocks (LABs) | 1,846 | — |
| Embedded Memory Bits | 1,669,248 | — |
| Maximum User I/Os | 426 | 426 |
| 封裝 | 672-ball FineLine BGA | 672-BBGA (FineLine BGA), 35 x 35 mm, 1.27 mm pitch |
| Package Code | F672 | — |
| Speed Grade | C6 | — |
| 工作溫度 | 0°C to +85°C (Commercial) | -40C to +85C (industrial grade, I7 suffix) |
| 供應電壓 | Core 1.5 V, I/O programmable | — |
| 安裝類型 | Surface Mount | Surface Mount (BGA) |
| RoHS 狀態 | [DATA_NEEDED: RoHS compliance status] | unknown |
| Maximum RAM Bits | — | 1,669,248 |
| DSP Blocks | — | [DATA_NEEDED: exact DSP block count] |
| Supply Voltage (VCCINT core) | — | 1.5 V |
| Logic Family | — | CMOS |
| Configuration Modes | — | Passive Serial, Passive Parallel, JTAG |
| Number of Pins / Balls | — | 672 |
| Clock Management PLLs | — | [DATA_NEEDED: PLL count] |
| Lead-Free / Finish | — | SnPb (e0 per Partstack datasheet extract) |
| MSL 等級 | — | unknown |
| Status | — | Last Time Buy (per distributor notices) |