EP1S20F672C7N vs EP1S20F672C7 Ikinahambing
Detalyadong pagkakahiwalay na pagkakahambing ng EP1S20F672C7N sa pamamagitan ng Intel at EP1S20F672C7 sa pamamagitan ng Intel. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.
Pagsanggunian na paghahambing
| Parametro | EP1S20F672C7N | EP1S20F672C7 |
|---|---|---|
| Brand | Intel | Intel |
| Kategorya | FPGA & CPLD | FPGA & CPLD |
| Katayuan ng Lifecycle | Obsolete | Huling Pagbili |
| Series | Stratix (first generation) | Stratix |
| Family | Stratix | Altera Stratix FPGA |
| Logic Elements (LEs) | 18,460 | 18,460 |
| Logic Cells | 18,460 | — |
| Configurable Logic Blocks (CLBs) | 2,132 | — |
| Embedded Memory (TriMatrix) | 1,669,248 bits (426 Kbit total) | — |
| DSP Blocks | 56 (dedicated 18x18 multipliers) | [DATA_NEEDED: DSP block count] |
| Maximum User I/O | 586 | — |
| I/O Banks | [DATA_NEEDED: I/O bank count] | — |
| PLLs | Up to 12 | — |
| Maximum Operating Frequency | 420.17 MHz | — |
| Core Voltage | 1.5 V | — |
| Process Technology | 130 nm CMOS | — |
| Packhaging | 672-FBGA (FineLine BGA) | 672-ball FineLine BGA (35 x 35 mm, 1.27 mm pitch) |
| Package Body Size | 35 mm x 35 mm | — |
| Ball Pitch | 1.27 mm | — |
| Temperature na Operasyon | 0°C to +85°C (commercial) | 0C to 85C (commercial) |
| Speed Grade | C7 (-7) | C7 |
| Uri ng Pagpapasok | Surface Mount | Surface Mount |
| Lead-Free / RoHS | Yes (lead-free finish, RoHS compliant) | — |
| Configuration Modes | PS, PPS, FPP, JTAG | JTAG, Passive Serial, Fast Passive Parallel, Active Serial |
| Level ng MSL | [DATA_NEEDED: moisture sensitivity level] | [DATA_NEEDED: MSL level] |
| Embedded Memory Bits | — | 1,669,248 |
| User I/O Pins | — | 426 |
| Logic Family | — | CMOS, SRAM-based |
| Core Supply Voltage | — | 1.5 V |
| Tindminan RoHS | — | unknown |
| Clock PLLs | — | Up to 10 |