EP1S25B672C7 vs EP1S20B672C7N Ikinahambing
Detalyadong pagkakahiwalay na pagkakahambing ng EP1S25B672C7 sa pamamagitan ng Intel at EP1S20B672C7N sa pamamagitan ng Intel. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.
Pagsanggunian na paghahambing
| Parametro | EP1S25B672C7 | EP1S20B672C7N |
|---|---|---|
| Brand | Intel | Intel |
| Kategorya | FPGA & CPLD | FPGA & CPLD |
| Katayuan ng Lifecycle | Obsolete | Obsolete |
| Family | Stratix | Stratix (original) |
| Logic Cells | 25,660 | — |
| Logic Array Blocks (LABs) | 2,566 | — |
| Embedded Memory (bits) | 1,944,576 | — |
| Maximum User I/O | 473 | 426 |
| Core Voltage | 1.5 V | — |
| Process Technology | 130 nm CMOS | 0.13 µm CMOS |
| Maximum Internal Frequency | 420.17 MHz | — |
| Number of PLLs | [DATA_NEEDED: PLL count] | — |
| Packhaging | 672-BGA, 35 x 35 mm, 1.27 mm pitch | — |
| Bilang ng Pin | 672 | — |
| Speed Grade | C7 (commercial, slowest bin) | -7 |
| Temperature na Operasyon | 0 C to 85 C | 0 °C to 85 °C (Commercial Extended) |
| Uri ng Pagpapasok | Surface Mount | Surface Mount (BGA) |
| Tindminan RoHS | [DATA_NEEDED: RoHS compliance] | [DATA_NEEDED: RoHS compliance] |
| Configuration Method | SRAM-based (volatile, requires config device) | — |
| Logic Family | CMOS | CMOS |
| DSP Blocks | [DATA_NEEDED: DSP block count] | — |
| Series | — | Stratix |
| Logic Elements (LEs) | — | 18,460 |
| LABs / CLBs | — | 1,846 |
| Embedded Memory Bits | — | 1,669,248 bits |
| Number of Pins / Balls | — | 672 |
| Package Type | — | 672-BBGA (Fine-pitch BGA, 35 × 35 mm, 1.27 mm pitch) |
| Supply Voltage (Core, VCCINT) | — | 1.5 V |
| Level ng MSL | — | 3 (per JEDEC J-STD-020) |
| Lead-Free | — | [DATA_NEEDED: lead-free status] |