EP1S25B672C7 vs EP1S20B672C7N 比較
詳細並排比較 EP1S25B672C7 由 Intel 與 EP1S20B672C7N 由 Intel. 比較關鍵規格、電氣參數、封裝、生命週期狀態、價格與供貨情況，以找出最符合您設計需求的元件。
規格比較
| 參數 | EP1S25B672C7 | EP1S20B672C7N |
|---|---|---|
| 品牌 | Intel | Intel |
| 類別 | FPGA & CPLD | FPGA & CPLD |
| 生命週期狀態 | Obsolete | Obsolete |
| Family | Stratix | Stratix (original) |
| Logic Cells | 25,660 | — |
| Logic Array Blocks (LABs) | 2,566 | — |
| Embedded Memory (bits) | 1,944,576 | — |
| Maximum User I/O | 473 | 426 |
| Core Voltage | 1.5 V | — |
| Process Technology | 130 nm CMOS | 0.13 µm CMOS |
| Maximum Internal Frequency | 420.17 MHz | — |
| Number of PLLs | [DATA_NEEDED: PLL count] | — |
| 封裝 | 672-BGA, 35 x 35 mm, 1.27 mm pitch | — |
| 腳位數 | 672 | — |
| Speed Grade | C7 (commercial, slowest bin) | -7 |
| 工作溫度 | 0 C to 85 C | 0 °C to 85 °C (Commercial Extended) |
| 安裝類型 | Surface Mount | Surface Mount (BGA) |
| RoHS 狀態 | [DATA_NEEDED: RoHS compliance] | [DATA_NEEDED: RoHS compliance] |
| Configuration Method | SRAM-based (volatile, requires config device) | — |
| Logic Family | CMOS | CMOS |
| DSP Blocks | [DATA_NEEDED: DSP block count] | — |
| Series | — | Stratix |
| Logic Elements (LEs) | — | 18,460 |
| LABs / CLBs | — | 1,846 |
| Embedded Memory Bits | — | 1,669,248 bits |
| Number of Pins / Balls | — | 672 |
| Package Type | — | 672-BBGA (Fine-pitch BGA, 35 × 35 mm, 1.27 mm pitch) |
| Supply Voltage (Core, VCCINT) | — | 1.5 V |
| MSL 等級 | — | 3 (per JEDEC J-STD-020) |
| Lead-Free | — | [DATA_NEEDED: lead-free status] |