EP1S40B956C6 vs EP1S30B956C6 Ikinahambing
Detalyadong pagkakahiwalay na pagkakahambing ng EP1S40B956C6 sa pamamagitan ng Intel at EP1S30B956C6 sa pamamagitan ng Altera. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.
Pagsanggunian na paghahambing
| Parametro | EP1S40B956C6 | EP1S30B956C6 |
|---|---|---|
| Brand | Intel | Altera |
| Kategorya | FPGA & CPLD | FPGA & CPLD |
| Katayuan ng Lifecycle | NRND | Obsolete |
| Family | Stratix | Stratix |
| Logic Elements / Cells | 41,250 | — |
| Logic Array Blocks (LABs) | 4,125 | 3,247 |
| CLB Equivalents / Registers | 46,970 | — |
| User I/O Pins | 683 | — |
| Packhaging | BGA-956 (956-BBGA, FCBGA) | 956-ball FCBGA (BGA-956), 40 x 40 mm, 1.27 mm pitch |
| Package Size | 40 x 40 mm | — |
| Ball Pitch | 1.27 mm | — |
| Speed Grade | 6 (commercial, slowest) | C6 |
| Core Supply Voltage | 1.5 V | — |
| Temperature na Operasyon | 0C to 85C | 0 C to 85 C (Commercial) |
| Logic Family | CMOS | — |
| Uri ng Pagpapasok | Surface Mount | Surface Mount |
| Process Technology | 0.13 um CMOS | 130 nm CMOS |
| Embedded Memory | TriMatrix (M512, M4K, M-RAM blocks) | — |
| DSP Blocks | Embedded multiplier blocks | Yes (Stratix DSP blocks) |
| PLLs | Multiple phase-locked loops | Up to 12 |
| Lead-Free / RoHS | Per Altera/Intel datasheet | — |
| Logic Elements (LEs) | — | 32,470 |
| Embedded Memory Bits | — | 3,317,184 (approximately 3.4 Mbit) |
| Maximum User I/O | — | 683 |
| Core Voltage (VCCINT) | — | 1.5 V |
| Maximum Internal Frequency | — | 450.05 MHz (per family datasheet) |
| Configuration Modes | — | Passive Serial (PS), Passive Parallel (PP), JTAG |
| Tindminan RoHS | — | Not confirmed - pre-RoHS part |
| Level ng MSL | — | [DATA_NEEDED: MSL level] |
| Lead-Free | — | Unknown |