EP1S40B956C6 vs EP1S40B956C6N Ikinahambing
Detalyadong pagkakahiwalay na pagkakahambing ng EP1S40B956C6 sa pamamagitan ng Intel at EP1S40B956C6N sa pamamagitan ng Intel. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.
Pagsanggunian na paghahambing
| Parametro | EP1S40B956C6 | EP1S40B956C6N |
|---|---|---|
| Brand | Intel | Intel |
| Kategorya | FPGA & CPLD | FPGA & CPLD |
| Katayuan ng Lifecycle | NRND | Obsolete |
| Family | Stratix | Altera Stratix (1st generation) |
| Logic Elements / Cells | 41,250 | — |
| Logic Array Blocks (LABs) | 4,125 | 4,125 |
| CLB Equivalents / Registers | 46,970 | — |
| User I/O Pins | 683 | — |
| Packhaging | BGA-956 (956-BBGA, FCBGA) | 956-ball FineLine BGA (FCBGA) |
| Package Size | 40 x 40 mm | — |
| Ball Pitch | 1.27 mm | 1.27 mm |
| Speed Grade | 6 (commercial, slowest) | C6 (commercial, mid-speed) |
| Core Supply Voltage | 1.5 V | — |
| Temperature na Operasyon | 0C to 85C | 0 °C to +85 °C (Commercial) |
| Logic Family | CMOS | — |
| Uri ng Pagpapasok | Surface Mount | Surface Mount |
| Process Technology | 0.13 um CMOS | 0.13 µm CMOS |
| Embedded Memory | TriMatrix (M512, M4K, M-RAM blocks) | 3,423,744 bits (~3.4 Mbit) |
| DSP Blocks | Embedded multiplier blocks | — |
| PLLs | Multiple phase-locked loops | — |
| Lead-Free / RoHS | Per Altera/Intel datasheet | — |
| Series | — | Stratix |
| Logic Elements (LEs) | — | 41,250 |
| Maximum User I/O | — | 683 |
| Volte ng Pagbibigay | — | 1.425 V to 1.575 V (1.5 V nominal) |
| Package Dimensions | — | 40 mm x 40 mm |
| Configuration Interface | — | JTAG (IEEE 1149.1), Passive Serial, Active Serial |
| Level ng MSL | — | [DATA_NEEDED: MSL rating] |
| Tindminan RoHS | — | [DATA_NEEDED: RoHS compliance] |