EP1S40F780C8N vs EP1S40F780I6N Ikinahambing
Detalyadong pagkakahiwalay na pagkakahambing ng EP1S40F780C8N sa pamamagitan ng Intel at EP1S40F780I6N sa pamamagitan ng Intel. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.
Pagsanggunian na paghahambing
| Parametro | EP1S40F780C8N | EP1S40F780I6N |
|---|---|---|
| Brand | Intel | Intel |
| Kategorya | FPGA & CPLD | FPGA & CPLD |
| Katayuan ng Lifecycle | Obsolete | Obsolete |
| Family | Stratix | — |
| Series | EP1S | Stratix |
| Logic Elements | 41,250 | 41,250 |
| Embedded Memory | 3,423,744 bits | — |
| Embedded Multipliers | 615 (18-bit x 18-bit) | Yes (per DSP block) |
| Packhaging | 780-ball FCBGA (FineLine BGA), 29 mm x 29 mm, 1 mm pitch | 780-FBGA (29 x 29 mm, 1.0 mm pitch) |
| Logic Family | CMOS | — |
| Supply Voltage (Core) | 1.5 V | — |
| Speed Grade | C8 (commercial) | — |
| Temperature na Operasyon | 0 °C to +85 °C | -40C to +100C (industrial) |
| I/O Standard Support | LVDS, LVTTL, LVCMOS, SSTL, HSTL, PCI, PCI-X | — |
| Maximum LVDS Data Rate | 840 Mbps | — |
| PLL Blocks | Up to 12 | — |
| Uri ng Memory | TriMatrix (MRAM, M512, M4K blocks) | — |
| External Memory Interface | DDR, DDR-II, QDR, SDRAM | — |
| Configuration Method | Passive serial, Fast passive parallel, JTAG | SRAM-based, volatile |
| Design Software | Quartus II | — |
| Tindminan RoHS | Compliant | Compliant |
| Uri ng Pagpapasok | Surface Mount (BGA) | Surface Mount |
| Logic Array Blocks (LABs) | — | 4,125 |
| Total RAM Bits | — | 3,423,744 |
| User I/O Pins | — | 615 |
| Core Voltage (VCCINT) | — | 1.425 V to 1.575 V |
| Number of I/O Banks | — | [DATA_NEEDED: number of I/O banks] |
| DSP Blocks | — | 12 |
| PLLs | — | [DATA_NEEDED: PLL count per Stratix handbook] |
| Level ng MSL | — | 3 |
| Lead Free | — | Yes |
| Process Node | — | 150 nm CMOS |