EP1S60F1020I6N vs EP1S60F1020C7 Ikinahambing

Detalyadong pagkakahiwalay na pagkakahambing ng EP1S60F1020I6N sa pamamagitan ng Altera at EP1S60F1020C7 sa pamamagitan ng Altera. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.

Pagsanggunian na paghahambing

Parametro EP1S60F1020I6N EP1S60F1020C7
Brand Altera Altera
Kategorya FPGA & CPLD FPGA & CPLD
Katayuan ng Lifecycle NRND Obsolete
Series Stratix Stratix
Family Stratix FPGA (1st generation) Stratix (EP1S60)
Logic Elements (LEs) 57,120 —
Logic Array Blocks (LABs) 5,712 —
Logic Cells 6,570 —
Total RAM Bits 5,215,104 —
User I/O Count 773 —
Hanay ng Temperature na Operasyon 0°C to 85°C (I6 grade) —
Volte ng Pagbibigay 1.425 V to 1.575 V (1.5 V nominal core) —
Process Node 0.13 µm CMOS —
Packhaging 1020-FBGA (33 x 33 mm, 1.0 mm pitch) 1020-BBGA, FCBGA, 33 x 33 mm, 1.0 mm pitch
Speed Grade 6 7
Temperature Grade I (Industrial) —
Uri ng Pagpapasok Surface Mount (BGA) Surface Mount
Level ng MSL [DATA_NEEDED: MSL level] 3 (per BGA moisture-sensitivity norms)
Tindminan RoHS Compliant Compliant (lead-free)
Logic Elements — 57,120
Total Memory Bits — 5,215,104
Maximum User I/O — 773
Logic Family — CMOS
Temperature na Operasyon — 0C to +85C (Commercial)
Core Supply Voltage — 1.5 V
Logic Cells / Logic Blocks — 6,570 (per datasheet Section I nomenclature)
DSP Blocks — Embedded dedicated multiplier / adder blocks
PLLs — Up to 12 enhanced PLLs per die
Configuration Method — Serial or parallel with optional decompression

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