EP1SGX25DF1020C4 vs EP1SGX25DF1020C6ESL Ikinahambing
Detalyadong pagkakahiwalay na pagkakahambing ng EP1SGX25DF1020C4 sa pamamagitan ng Intel at EP1SGX25DF1020C6ESL sa pamamagitan ng Altera. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.
Altera
EP1SGX25DF1020C6ESL - Stratix GX FPGA, 25K LE, 1020-BGA | Altera/Intel
EP1SGX25DF1020C6ESL ObsoletePagsanggunian na paghahambing
| Parametro | EP1SGX25DF1020C4 | EP1SGX25DF1020C6ESL |
|---|---|---|
| Brand | Intel | Altera |
| Kategorya | FPGA & CPLD | FPGA & CPLD |
| Katayuan ng Lifecycle | Obsolete | Obsolete |
| Family | Stratix GX | Stratix GX |
| Series | EP1SGX25 | — |
| Logic Elements | 25,660 | 25,660 |
| Embedded Memory | 1,944 Kbit | — |
| DSP Blocks | 80 (18x18-bit multipliers) | Yes (embedded DSP blocks) |
| Transceiver Channels | 20 (up to 3.125 Gbps) | — |
| Core Voltage | 1.5 V | 1.5 V |
| Speed Grade | C4 | C6 |
| Temperature na Operasyon | 0C to +85C (commercial) | — |
| Packhaging | 1020-ball FineLine BGA (FBGA) | 1020-BBGA (FineLine BGA) |
| Process | 0.13 um CMOS SRAM | — |
| I/O Standards | LVTTL, LVCMOS, LVDS, SSTL, HSTL | — |
| PLLs | Yes (clock management) | — |
| Configuration | JTAG, Passive Serial, Active Serial | — |
| Tindminan RoHS | Compliant | [DATA_NEEDED: RoHS status] |
| Uri ng Pagpapasok | Surface Mount (BGA) | Surface Mount |
| Total RAM Bits | — | 1,944,576 bits |
| User I/O Pins | — | 607 |
| LABs/CLBs | — | 2,566 |
| Temperature ng Junction na Operasyon | — | 0 C to 85 C |
| Configuration Method | — | Passive Serial / Fast Passive Parallel / JTAG |
| Process Node | — | 0.13 um CMOS |
| Transceivers | — | Embedded multi-gigabit transceivers (per Stratix GX family) |
| I/O Standards Supported | — | LVTTL, LVCMOS, SSTL, HSTL, LVDS (per family) |