EP1SGX25DF1020C6ESL vs EP1SGX25DF1020C6B Ikinahambing

Detalyadong pagkakahiwalay na pagkakahambing ng EP1SGX25DF1020C6ESL sa pamamagitan ng Altera at EP1SGX25DF1020C6B sa pamamagitan ng Altera. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.

Pagsanggunian na paghahambing

Parametro EP1SGX25DF1020C6ESL EP1SGX25DF1020C6B
Brand Altera Altera
Kategorya FPGA & CPLD FPGA & CPLD
Katayuan ng Lifecycle Obsolete NRND
Family Stratix GX EP1SGX25
Logic Elements 25,660 25,660
Total RAM Bits 1,944,576 bits —
User I/O Pins 607 —
LABs/CLBs 2,566 —
Packhaging 1020-BBGA (FineLine BGA) 1020-BBGA (33 × 33 mm, 1.0 mm pitch)
Core Voltage 1.5 V —
Temperature ng Junction na Operasyon 0 C to 85 C —
Uri ng Pagpapasok Surface Mount Surface Mount (BGA)
Tindminan RoHS [DATA_NEEDED: RoHS status] [DATA_NEEDED: RoHS status]
Configuration Method Passive Serial / Fast Passive Parallel / JTAG —
Process Node 0.13 um CMOS —
Transceivers Embedded multi-gigabit transceivers (per Stratix GX family) Embedded high-speed serial transceivers (multi-gigabit)
DSP Blocks Yes (embedded DSP blocks) Hardware multipliers / DSP blocks
Speed Grade C6 C6
I/O Standards Supported LVTTL, LVCMOS, SSTL, HSTL, LVDS (per family) —
Series — Stratix GX
Total Memory Bits — 1,944,576
User I/O Count — 607
Supply Voltage (Core) — 1.5 V
Temperature na Operasyon — 0 °C to 85 °C (Commercial)
Level ng MSL — [DATA_NEEDED: MSL rating]
Lead-Free — Yes (per DigiChip package note)
PLLs — On-chip phase-locked loops for clock management
External Memory Support — DDR, DDR2, SDR, QDR, QDRII SRAM
Hard IP — PCI Express (per Stratix GX family)

Mga Datasheets at Resources

Tingnan ang Lahat ng mga Produkto Lumikha ng BOM Hilingin ang Kita