EP1SGX40DF1020C7ES vs EP1SGX40DF1020C5ES Ikinahambing

Detalyadong pagkakahiwalay na pagkakahambing ng EP1SGX40DF1020C7ES sa pamamagitan ng Altera at EP1SGX40DF1020C5ES sa pamamagitan ng Intel. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.

Intel
EP1SGX40DF1020C5ES EP1SGX40DF1020C5ES - 41,250-Cell Stratix GX FPGA | Intel

EP1SGX40DF1020C5ES - 41,250-Cell Stratix GX FPGA | Intel

EP1SGX40DF1020C5ES ✓ Nakahanda

Pagsanggunian na paghahambing

Parametro EP1SGX40DF1020C7ES EP1SGX40DF1020C5ES
Brand Altera Intel
Kategorya FPGA & CPLD FPGA & CPLD
Katayuan ng Lifecycle NRND Aktibo
Family Stratix GX —
Logic Elements 41,250 —
Logic Family CMOS Stratix GX
Process Technology 130 nm 130 nm
Volte ng Pagbibigay 1.5 V (core) 1.5 V
Packhaging FBGA-1020 (33 x 33 mm, 1.0 mm pitch) —
Terminal Form Ball Ball
Package Shape Square —
Number of Pins/Terminals 1020 —
Temperature na Operasyon 0 C to 85 C (32 F to 185 F) 0 C to 85 C
Temperature Grade Commercial (speed grade C7) —
Uri ng Pagpapasok Surface Mount (BGA) —
Combinatorial Delay 9.48 ns per CLB —
Maksimum na Taktiko ng Oras 4385.97 MHz (internal) —
Manufacturer Altera (now Intel PSG) —
Tindminan RoHS [DATA_NEEDED: RoHS status] unknown
Product Type — Field-Programmable Gate Array (FPGA)
Logic Technology — CMOS
Logic Cells — 41,250 cells
Logic Array Blocks — 4,125 LABs
Configurable I/O Connections — 624 input and 624 output connections
Reported Maximum Frequency — 5,000 MHz
Reported Maximum CLB Combinatorial Delay — 7.49 ns
Alternative Listed Maximum Clock Frequency — 6 MHz
Terminal Count — 1,020 pins
Package Type — FC-FBGA-1020
Package Dimensions — 33 mm x 33 mm
Ball Pitch — 1 mm
Mounting Configuration — Surface-mount ball grid array
Package Code — BGA
Configuration Method — [DATA_NEEDED: configuration method]
REACH Status — unknown
AEC-Q100 Qualification — unknown

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