EP1SGX40DF1020C7ES vs EP1SGX40DF1020C5ES 比較

詳細並排比較 EP1SGX40DF1020C7ES 由 Altera 與 EP1SGX40DF1020C5ES 由 Intel. 比較關鍵規格、電氣參數、封裝、生命週期狀態、價格與供貨情況，以找出最符合您設計需求的元件。

Altera

EP1SGX40DF1020C7ES - Stratix GX FPGA, 41.25K Cells, FBGA-1020 | Altera

EP1SGX40DF1020C7ES Nrnd

Intel

EP1SGX40DF1020C5ES ✓ 啟用中

參數	EP1SGX40DF1020C7ES	EP1SGX40DF1020C5ES
品牌	Altera	Intel
類別	FPGA & CPLD	FPGA & CPLD
生命週期狀態	NRND	啟用中
Family	Stratix GX	—
Logic Elements	41,250	—
Logic Family	CMOS	Stratix GX
Process Technology	130 nm	130 nm
供應電壓	1.5 V (core)	1.5 V
封裝	FBGA-1020 (33 x 33 mm, 1.0 mm pitch)	—
Terminal Form	Ball	Ball
Package Shape	Square	—
Number of Pins/Terminals	1020	—
工作溫度	0 C to 85 C (32 F to 185 F)	0 C to 85 C
Temperature Grade	Commercial (speed grade C7)	—
安裝類型	Surface Mount (BGA)	—
Combinatorial Delay	9.48 ns per CLB	—
最大時脈頻率	4385.97 MHz (internal)	—
Manufacturer	Altera (now Intel PSG)	—
RoHS 狀態	[DATA_NEEDED: RoHS status]	unknown
Product Type	—	Field-Programmable Gate Array (FPGA)
Logic Technology	—	CMOS
Logic Cells	—	41,250 cells
Logic Array Blocks	—	4,125 LABs
Configurable I/O Connections	—	624 input and 624 output connections
Reported Maximum Frequency	—	5,000 MHz
Reported Maximum CLB Combinatorial Delay	—	7.49 ns
Alternative Listed Maximum Clock Frequency	—	6 MHz
Terminal Count	—	1,020 pins
Package Type	—	FC-FBGA-1020
Package Dimensions	—	33 mm x 33 mm
Ball Pitch	—	1 mm
Mounting Configuration	—	Surface-mount ball grid array
Package Code	—	BGA
Configuration Method	—	[DATA_NEEDED: configuration method]
REACH Status	—	unknown
AEC-Q100 Qualification	—	unknown