EP20K100CT144C7ES vs EP20K100CT144C9 Ikinahambing
Detalyadong pagkakahiwalay na pagkakahambing ng EP20K100CT144C7ES sa pamamagitan ng Altera at EP20K100CT144C9 sa pamamagitan ng Altera. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.
Altera
EP20K100CT144C7ES - APEX-20K 100K Gate FPGA, 93 I/O, 144-LQFP | Altera
EP20K100CT144C7ES NrndPagsanggunian na paghahambing
| Parametro | EP20K100CT144C7ES | EP20K100CT144C9 |
|---|---|---|
| Brand | Altera | Altera |
| Kategorya | FPGA & CPLD | FPGA & CPLD |
| Katayuan ng Lifecycle | NRND | Obsolete |
| Series | APEX-20K | — |
| Core Voltage (VCCINT) | 2.375 V to 2.625 V | 2.5 V |
| Typical Gate Count | 100,000 gates | — |
| Logic Elements | 4,160 | — |
| Total RAM Bits | 53,248 bits | — |
| User I/O Pins | 93 | — |
| Packhaging | 144-LQFP (20x20 mm) | 144-LQFP |
| Temperature na Operasyon | 0C to +85C (Commercial) | 0C to +85C (Commercial) |
| Process Technology | 0.18 µm CMOS | 0.22 um CMOS |
| Uri ng Pagpapasok | Surface Mount | Surface Mount |
| MultiVolt I/O Levels | 1.8 V, 2.5 V, 3.3 V, 5 V | — |
| Configuration Interface | IEEE 1149.1 JTAG | — |
| Level ng MSL | 3 | — |
| Tindminan RoHS | Compliant (per Besenchips listing) | [DATA_NEEDED: rohs status] |
| Lead-Free | Yes | — |
| Family | — | APEX-20K |
| Device Logic Elements | — | 4,160 |
| Typical Gates | — | 100,000 |
| Embedded Memory (RAM bits) | — | 53,248 |
| Maximum User I/O | — | 93 |
| Speed Grade | — | -9 |
| I/O Voltage (VCCIO) | — | 3.3 V |
| Number of PLLs | — | 4 |
| Configuration Method | — | SRAM / JTAG (IEEE 1149.1) |