EP20K100CT144C7ES vs EP20K100CT144C9 比較
詳細並排比較 EP20K100CT144C7ES 由 Altera 與 EP20K100CT144C9 由 Altera. 比較關鍵規格、電氣參數、封裝、生命週期狀態、價格與供貨情況，以找出最符合您設計需求的元件。
Altera
EP20K100CT144C7ES - APEX-20K 100K Gate FPGA, 93 I/O, 144-LQFP | Altera
EP20K100CT144C7ES Nrnd規格比較
| 參數 | EP20K100CT144C7ES | EP20K100CT144C9 |
|---|---|---|
| 品牌 | Altera | Altera |
| 類別 | FPGA & CPLD | FPGA & CPLD |
| 生命週期狀態 | NRND | Obsolete |
| Series | APEX-20K | — |
| Core Voltage (VCCINT) | 2.375 V to 2.625 V | 2.5 V |
| Typical Gate Count | 100,000 gates | — |
| Logic Elements | 4,160 | — |
| Total RAM Bits | 53,248 bits | — |
| User I/O Pins | 93 | — |
| 封裝 | 144-LQFP (20x20 mm) | 144-LQFP |
| 工作溫度 | 0C to +85C (Commercial) | 0C to +85C (Commercial) |
| Process Technology | 0.18 µm CMOS | 0.22 um CMOS |
| 安裝類型 | Surface Mount | Surface Mount |
| MultiVolt I/O Levels | 1.8 V, 2.5 V, 3.3 V, 5 V | — |
| Configuration Interface | IEEE 1149.1 JTAG | — |
| MSL 等級 | 3 | — |
| RoHS 狀態 | Compliant (per Besenchips listing) | [DATA_NEEDED: rohs status] |
| Lead-Free | Yes | — |
| Family | — | APEX-20K |
| Device Logic Elements | — | 4,160 |
| Typical Gates | — | 100,000 |
| Embedded Memory (RAM bits) | — | 53,248 |
| Maximum User I/O | — | 93 |
| Speed Grade | — | -9 |
| I/O Voltage (VCCIO) | — | 3.3 V |
| Number of PLLs | — | 4 |
| Configuration Method | — | SRAM / JTAG (IEEE 1149.1) |