EP20K100EBC356-3N vs EP20K100EFC144-1 Ikinahambing
Detalyadong pagkakahiwalay na pagkakahambing ng EP20K100EBC356-3N sa pamamagitan ng Altera at EP20K100EFC144-1 sa pamamagitan ng Intel. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.
Pagsanggunian na paghahambing
| Parametro | EP20K100EBC356-3N | EP20K100EFC144-1 |
|---|---|---|
| Brand | Altera | Intel |
| Kategorya | FPGA & CPLD | FPGA & CPLD |
| Katayuan ng Lifecycle | Obsolete | NRND |
| Series | APEX-20KE | — |
| Family | APEX 20K | — |
| Logic Elements / Cells | 4160 | — |
| System Gates | 100,000 | — |
| Embedded Memory (bits) | 53,248 | — |
| Embedded System Blocks (ESBs) | 26 | Yes (memory + dedicated logic) |
| Maximum User I/Os | 246 | — |
| Bilang ng Pins | 356 | — |
| Packhaging | 356-LBGA (Ball Grid Array) | — |
| Package Dimensions | 45 x 45 mm | — |
| Ball Pitch | 1.27 mm | — |
| Process Technology | 0.22 µm CMOS | 0.15-µm all-layer copper |
| Core Supply Voltage | 1.8 V | — |
| Propagation Delay | 1.6 ns (speed grade -3N) | 1.6 ns |
| Maximum Internal Frequency | 250 MHz | — |
| Temperature na Operasyon | 0 °C to +85 °C | 0 °C to 85 °C (commercial) |
| Uri ng Pagpapasok | Surface Mount | Surface Mount |
| Programmable Interface | JTAG (IEEE 1149.1) | — |
| I/O Standards Supported | LVCMOS, LVTTL, PCI, SSTL-2/3, GTL+ | — |
| Tindminan RoHS | [DATA_NEEDED: rohs_status] | [DATA_NEEDED: RoHS compliance] |
| Device Family | — | APEX 20KE |
| Device Type | — | FPGA (Field Programmable Gate Array) |
| Typical Gates | — | 100,000 |
| Maximum System Gates | — | 263,000 |
| Logic Elements | — | 4,160 |
| User I/Os | — | 93 |
| PLLs | — | 4 |
| Package Type | — | 144-ball FBGA (13x13 mm, 1.0 mm pitch) |
| Core Voltage (VCCINT) | — | 1.71 V to 1.89 V |
| I/O Voltage Support | — | 1.8 V / 2.5 V / 3.3 V (multiVolt I/O) |
| Configuration Method | — | SRAM (volatile) - external boot PROM required |
| Boundary-Scan Support | — | IEEE 1149.1 (JTAG) |