EP20K100EBC652-2X vs EP20K200EBC652-3 Ikinahambing
Detalyadong pagkakahiwalay na pagkakahambing ng EP20K100EBC652-2X sa pamamagitan ng Altera at EP20K200EBC652-3 sa pamamagitan ng Intel. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.
Pagsanggunian na paghahambing
| Parametro | EP20K100EBC652-2X | EP20K200EBC652-3 |
|---|---|---|
| Brand | Altera | Intel |
| Kategorya | FPGA & CPLD | FPGA & CPLD |
| Katayuan ng Lifecycle | Obsolete | Obsolete |
| Family | APEX 20KE | APEX-20KE |
| Typical Gates | 100,000 | — |
| Maximum System Gates | 263,000 | — |
| Logic Elements | 4,160 | — |
| Embedded System Blocks (ESBs) | 26 | Yes (dual-port RAM / ROM / CAM) |
| Maximum RAM Bits | 53,248 | — |
| Maximum User I/O Pins | 246 | 376 |
| Supply Voltage - Core | 1.8 V | — |
| Supply Voltage - I/O | 1.8 V / 2.5 V / 3.3 V | — |
| Packhaging | 652-ball BGA (EBC652) | 652-ball FineLine BGA (top-side, 1.27 mm pitch) |
| Speed Grade | -2 (faster commercial) | -3 |
| Process Technology | 0.18 µm CMOS, SRAM-based | — |
| Temperature na Operasyon | 0C to +85C (commercial) | 0C to +85C (EBC - Enhanced Commercial) |
| Uri ng Pagpapasok | Surface Mount | Surface Mount |
| Configuration Method | Passive Serial / Passive Parallel / JTAG (EPC) | — |
| Clock Resources | Up to 4 DLLs, multiple global clocks | — |
| Tindminan RoHS | [DATA_NEEDED: RoHS status] | Not RoHS (non-lead-free variant) |
| Logic Elements (LEs) | — | 8,320 |
| Logic Array Blocks (LABs) | — | 832 |
| Total RAM Bits | — | 106,496 |
| PLLs | — | 4 |
| Configuration Mode | — | JTAG / PS / Passive-serial / Passive-parallel |
| Process Node | — | [DATA_NEEDED: process node] |
| Core Voltage | — | [DATA_NEEDED: core voltage] |
| Katayuan ng Lifecycle | — | Obsolete - last time-buy period closed |