EP20K100EBC652-2X vs EP20K200EBC652-3 比較
詳細並排比較 EP20K100EBC652-2X 由 Altera 與 EP20K200EBC652-3 由 Intel. 比較關鍵規格、電氣參數、封裝、生命週期狀態、價格與供貨情況，以找出最符合您設計需求的元件。
規格比較
| 參數 | EP20K100EBC652-2X | EP20K200EBC652-3 |
|---|---|---|
| 品牌 | Altera | Intel |
| 類別 | FPGA & CPLD | FPGA & CPLD |
| 生命週期狀態 | Obsolete | Obsolete |
| Family | APEX 20KE | APEX-20KE |
| Typical Gates | 100,000 | — |
| Maximum System Gates | 263,000 | — |
| Logic Elements | 4,160 | — |
| Embedded System Blocks (ESBs) | 26 | Yes (dual-port RAM / ROM / CAM) |
| Maximum RAM Bits | 53,248 | — |
| Maximum User I/O Pins | 246 | 376 |
| Supply Voltage - Core | 1.8 V | — |
| Supply Voltage - I/O | 1.8 V / 2.5 V / 3.3 V | — |
| 封裝 | 652-ball BGA (EBC652) | 652-ball FineLine BGA (top-side, 1.27 mm pitch) |
| Speed Grade | -2 (faster commercial) | -3 |
| Process Technology | 0.18 µm CMOS, SRAM-based | — |
| 工作溫度 | 0C to +85C (commercial) | 0C to +85C (EBC - Enhanced Commercial) |
| 安裝類型 | Surface Mount | Surface Mount |
| Configuration Method | Passive Serial / Passive Parallel / JTAG (EPC) | — |
| Clock Resources | Up to 4 DLLs, multiple global clocks | — |
| RoHS 狀態 | [DATA_NEEDED: RoHS status] | Not RoHS (non-lead-free variant) |
| Logic Elements (LEs) | — | 8,320 |
| Logic Array Blocks (LABs) | — | 832 |
| Total RAM Bits | — | 106,496 |
| PLLs | — | 4 |
| Configuration Mode | — | JTAG / PS / Passive-serial / Passive-parallel |
| Process Node | — | [DATA_NEEDED: process node] |
| Core Voltage | — | [DATA_NEEDED: core voltage] |
| 生命週期狀態 | — | Obsolete - last time-buy period closed |