EP20K100EFC324-1N vs EP20K30EFC324-1X Ikinahambing

Detalyadong pagkakahiwalay na pagkakahambing ng EP20K100EFC324-1N sa pamamagitan ng Altera at EP20K30EFC324-1X sa pamamagitan ng Intel. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.

Pagsanggunian na paghahambing

Parametro EP20K100EFC324-1N EP20K30EFC324-1X
Brand Altera Intel
Kategorya FPGA & CPLD FPGA & CPLD
Katayuan ng Lifecycle Obsolete Obsolete
Family APEX-20KE APEX-20K® (MultiCore™ architecture)
Device Type FPGA (Field Programmable Gate Array) —
Logic Elements (LEs) 4160 1,200
Typical Gates 100,000 —
Maximum User I/O 246 128
Embedded System Blocks (ESBs) 53248 bits —
Packhaging 324-BGA (FineLine BGA) 324-ball FBGA (FineLine BGA), 19x19 mm
Temperature na Operasyon 0 C to 85 C —
Propagation Delay 1.6 ns —
Internal Operating Frequency 250 MHz —
Core Voltage 1.8 V —
I/O Standard Support LVDS, SSTL, HSTL, LVTTL, LVCMOS LVDS, LVTTL, LVCMOS, PCI, SSTL
Process Technology 0.15 µm all-layer copper CMOS 0.22 µm CMOS
JTAG Support IEEE 1149.1 boundary-scan —
Programming Technology SRAM-based (volatile, requires configuration device) —
MultiVolt I/O 1.8 V core with 3.3 V / 5.0 V I/O support —
Series — APEX 20KE
Typical Gate Count — 30,000 gates
Embedded Memory (RAM bits) — 24,576
Dedicated Inputs — 4
Core Supply Voltage — 1.71 V to 1.89 V (1.8 V nominal)
Logic Delay (tPD) — 1.91 ns
Maksimum na Taktiko ng Oras — 909 MHz (internal), 160 MHz (I/O per partstack summary)
Uri ng Pagpapasok — Surface Mount
Configuration Method — Passive Serial, JTAG, Fast Passive Parallel
PLLs — 4
Tindminan RoHS — Compliant
Operating Temperature Grade — Commercial (0 °C to +85 °C) per package suffix interpretation; industrial on -1X grade [DATA_NEEDED: exact Tj range]

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