EP20K100EFC324-2X vs EP20K100EFC324-1N Ikinahambing

Detalyadong pagkakahiwalay na pagkakahambing ng EP20K100EFC324-2X sa pamamagitan ng Intel at EP20K100EFC324-1N sa pamamagitan ng Altera. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.

Pagsanggunian na paghahambing

Parametro EP20K100EFC324-2X EP20K100EFC324-1N
Brand Intel Altera
Kategorya FPGA & CPLD FPGA & CPLD
Katayuan ng Lifecycle NRND Obsolete
Family APEX 20KE APEX-20KE
Device Type SPLD / FPGA (Field Programmable Gate Array) FPGA (Field Programmable Gate Array)
System Gates 100,000 gates —
Logic Elements / Cells 4,160 —
Total RAM Bits 53,248 bits —
LABs / CLBs 416 —
Maximum User I/Os 246 —
Number of I/O Banks 8 (per APEX 20KE family) —
Propagation Delay 1.6 ns 1.6 ns
Internal Operating Frequency Up to 250 MHz 250 MHz
Core Supply Voltage (VCCINT) 1.8 V —
I/O Supply Voltage (VCCIO) MultiVolt: 1.8 V / 2.5 V / 3.3 V —
Process Technology 0.22 µm CMOS (all-layer copper metal) 0.15 µm all-layer copper CMOS
Speed Grade -2X —
Packhaging 324-ball FBGA (FineLine BGA), 19x19 mm, 1.27 mm pitch 324-BGA (FineLine BGA)
Uri ng Pagpapasok Surface Mount —
Temperature na Operasyon 0 °C to 85 °C (Commercial) 0 C to 85 C
Programming Interface IEEE 1149.1 JTAG —
Configuration Modes Passive Serial, Passive Parallel, JTAG, Altera configuration EPROM —
Tindminan RoHS [DATA_NEEDED: confirm against lot-specific documentation] —
Logic Elements (LEs) — 4160
Typical Gates — 100,000
Maximum User I/O — 246
Embedded System Blocks (ESBs) — 53248 bits
Core Voltage — 1.8 V
I/O Standard Support — LVDS, SSTL, HSTL, LVTTL, LVCMOS
JTAG Support — IEEE 1149.1 boundary-scan
Programming Technology — SRAM-based (volatile, requires configuration device)
MultiVolt I/O — 1.8 V core with 3.3 V / 5.0 V I/O support

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