EP20K100FC324-1V vs EP20K100EFC324-1N Ikinahambing
Detalyadong pagkakahiwalay na pagkakahambing ng EP20K100FC324-1V sa pamamagitan ng Intel at EP20K100EFC324-1N sa pamamagitan ng Altera. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.
Pagsanggunian na paghahambing
| Parametro | EP20K100FC324-1V | EP20K100EFC324-1N |
|---|---|---|
| Brand | Intel | Altera |
| Kategorya | FPGA & CPLD | FPGA & CPLD |
| Katayuan ng Lifecycle | Obsolete | Obsolete |
| Series | APEX-20K® | — |
| Number of Logic Elements / Cells | 4160 | — |
| Total RAM Bits | 53248 | — |
| Number of Gates (typical) | 100000 | — |
| Number of I/O | 252 | — |
| Number of LABs/CLBs | [DATA_NEEDED: number of Logic Array Blocks] | — |
| Number of EABs | [DATA_NEEDED: number of Embedded Array Blocks] | — |
| Supply Voltage - Core (VCCINT) | 2.375 V to 2.625 V | — |
| Supply Voltage - I/O (VCCIO) | 3.0 V / 3.3 V / 5.0 V tolerant (per I/O standard) | — |
| Speed Grade | -1V (commercial) | — |
| Temperature na Operasyon | 0C to +85C (commercial) | 0 C to 85 C |
| Uri ng Pagpapasok | Surface Mount | — |
| Packhaging / Kaso | 324-FBGA (FineLine BGA, 19x19 mm) | — |
| Supplier Device Package | 324-FBGA | — |
| Number of PLLs | 4 | — |
| I/O Standards Supported | LVCMOS, LVTTL, PCI, SSTL, GTL+, HSTL | — |
| Architecture | MultiCore (LUT + product-term + embedded memory) | — |
| Programming Interface | JTAG (IEEE 1149.1) / in-system | — |
| Tindminan RoHS | [DATA_NEEDED: RoHS compliance] | — |
| Family | — | APEX-20KE |
| Device Type | — | FPGA (Field Programmable Gate Array) |
| Logic Elements (LEs) | — | 4160 |
| Typical Gates | — | 100,000 |
| Maximum User I/O | — | 246 |
| Embedded System Blocks (ESBs) | — | 53248 bits |
| Packhaging | — | 324-BGA (FineLine BGA) |
| Propagation Delay | — | 1.6 ns |
| Internal Operating Frequency | — | 250 MHz |
| Core Voltage | — | 1.8 V |
| I/O Standard Support | — | LVDS, SSTL, HSTL, LVTTL, LVCMOS |
| Process Technology | — | 0.15 µm all-layer copper CMOS |
| JTAG Support | — | IEEE 1149.1 boundary-scan |
| Programming Technology | — | SRAM-based (volatile, requires configuration device) |
| MultiVolt I/O | — | 1.8 V core with 3.3 V / 5.0 V I/O support |