EP20K200CB652C7ES vs EP20K200CF484C7ES Ikinahambing
Detalyadong pagkakahiwalay na pagkakahambing ng EP20K200CB652C7ES sa pamamagitan ng Altera at EP20K200CF484C7ES sa pamamagitan ng Intel. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.
Altera
EP20K200CB652C7ES - APEX 20K 200K FPGA 652-BGA | Altera/Intel
EP20K200CB652C7ES ⚠ Huling Pagbili
Pagsanggunian na paghahambing
| Parametro | EP20K200CB652C7ES | EP20K200CF484C7ES |
|---|---|---|
| Brand | Altera | Intel |
| Kategorya | FPGA & CPLD | FPGA & CPLD |
| Katayuan ng Lifecycle | Huling Pagbili | NRND |
| Family | APEX 20K | APEX-20KC |
| Logic Elements | 8,320 | — |
| Embedded System Block (ESB) RAM | 106,496 bits | — |
| Maximum User I/O Pins | [DATA_NEEDED: maximum user I/O count for 652-BGA] | — |
| Core Voltage (VCCINT) | 1.8 V | — |
| I/O Voltage (VCCIO) | 1.8 V / 2.5 V / 3.3 V / 5.0 V (MultiVolt) | — |
| Speed Grade | -7 | C7 (7 ns) |
| Operating Temperature (Commercial) | 0 °C to +85 °C | — |
| Packhaging | 652-BGA | — |
| Uri ng Pagpapasok | Surface Mount | Surface Mount |
| Configuration Method | SRAM (volatile, requires external PROM on power-up) | — |
| PLL Count | Up to 8 | — |
| Supported I/O Standards | LVTTL, LVCMOS, PCI, GTL+, SSTL, LVDS | — |
| JTAG (IEEE 1149.1) | Yes (boundary-scan) | — |
| Configuration Device Compatibility | EPC2, EPC8, EPC16, EPC64, microprocessor | — |
| Tindminan RoHS | [DATA_NEEDED: RoHS compliance status] | [DATA_NEEDED: rohs_status] |
| Level ng MSL | [DATA_NEEDED: moisture sensitivity level] | — |
| Series | — | APEX 20KC |
| Logic Elements / Cells | — | 8,320 |
| Typical Gates | — | 200,000 |
| Number of LABs/CLBs | — | 376 |
| Total RAM Bits | — | 106,496 |
| Number of I/O | — | 377 (max) |
| Voltage - Supply | — | 1.8 V core |
| Temperature na Operasyon | — | 0C to +85C (commercial) |
| Packhaging / Kaso | — | 484-BBGA (FineLine BGA) |
| Process Technology | — | 0.18 µm CMOS |
| Silicon Status | — | ES (Engineering Sample) |
| Maximum Internal Frequency | — | 375.94 MHz |
| Number of PLLs | — | [DATA_NEEDED: pll_count] |