EP20K200CF484C9N vs EP20K200CF484C7N Ikinahambing
Detalyadong pagkakahiwalay na pagkakahambing ng EP20K200CF484C9N sa pamamagitan ng Altera at EP20K200CF484C7N sa pamamagitan ng Altera. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.
Altera
EP20K200CF484C7N - APEX-20K 200K Gates FPGA 484-FBGA | Intel/Altera
EP20K200CF484C7N ObsoletePagsanggunian na paghahambing
| Parametro | EP20K200CF484C9N | EP20K200CF484C7N |
|---|---|---|
| Brand | Altera | Altera |
| Kategorya | FPGA & CPLD | FPGA & CPLD |
| Katayuan ng Lifecycle | Obsolete | Obsolete |
| Family | APEX 20KC | — |
| Device Type | FPGA (Field-Programmable Gate Array) | — |
| Typical Gates | 200,000 | — |
| Logic Elements | 8,320 | — |
| Embedded System Block (ESB) Bits | 106,496 | — |
| Maximum User I/O | 376 | — |
| Maksimum na Taktiko ng Oras | 250 MHz | — |
| Process Technology | 0.15 um CMOS | — |
| Core Supply Voltage (VCCINT) | 1.8 V | — |
| I/O Supply Voltage (VCCIO) | 3.3 V / 2.5 V / 1.8 V / 1.5 V (MultiVolt) | — |
| Packhaging | 484-pin FineLine BGA (FBGA) | — |
| Speed Grade | C9 (250 MHz) | — |
| Temperature Grade | Industrial (0C to +85C) | — |
| Uri ng Pagpapasok | Surface Mount (BGA) | Surface Mount |
| Configuration Scheme | SRAM-based, supports passive serial/parallel and JTAG | — |
| Level ng MSL | 3 (per JEDEC J-STD-020) | — |
| Tindminan RoHS | Compliant | [DATA_NEEDED: RoHS compliance status] |
| Series | — | APEX-20K |
| Logic Elements / Cells | — | 8,320 |
| Total RAM Bits | — | 106,496 |
| Number of Gates (typical) | — | 200,000 |
| Number of I/O | — | 382 |
| Voltage - Supply (VCCINT) | — | 1.71 V to 1.89 V |
| Packhaging / Kaso | — | 484-BBGA (FineLine BGA) |
| Supplier Device Package | — | 484-FBGA (23x23 mm) |
| Temperature na Operasyon | — | 0C to +85C (commercial grade) |
| Number of PLLs | — | 4 |
| Embedded Array Blocks (EABs) | — | Configurable as RAM/ROM/FIFO |
| Programmable Logic Blocks | — | APEX LAB architecture |
| MultiVolt I/O Support | — | 1.8V / 2.5V / 3.3V / 5V |
| Configuration Method | — | SRAM-based, in-system reconfigurable |
| Katayuan ng Lifecycle | — | Obsolete (Altera/Intel APEX-20K family EOL) |