EP20K200CF484C9N vs EP20K200CF484C7N 比較
詳細並排比較 EP20K200CF484C9N 由 Altera 與 EP20K200CF484C7N 由 Altera. 比較關鍵規格、電氣參數、封裝、生命週期狀態、價格與供貨情況，以找出最符合您設計需求的元件。
Altera
EP20K200CF484C7N - APEX-20K 200K Gates FPGA 484-FBGA | Intel/Altera
EP20K200CF484C7N Obsolete規格比較
| 參數 | EP20K200CF484C9N | EP20K200CF484C7N |
|---|---|---|
| 品牌 | Altera | Altera |
| 類別 | FPGA & CPLD | FPGA & CPLD |
| 生命週期狀態 | Obsolete | Obsolete |
| Family | APEX 20KC | — |
| Device Type | FPGA (Field-Programmable Gate Array) | — |
| Typical Gates | 200,000 | — |
| Logic Elements | 8,320 | — |
| Embedded System Block (ESB) Bits | 106,496 | — |
| Maximum User I/O | 376 | — |
| 最大時脈頻率 | 250 MHz | — |
| Process Technology | 0.15 um CMOS | — |
| Core Supply Voltage (VCCINT) | 1.8 V | — |
| I/O Supply Voltage (VCCIO) | 3.3 V / 2.5 V / 1.8 V / 1.5 V (MultiVolt) | — |
| 封裝 | 484-pin FineLine BGA (FBGA) | — |
| Speed Grade | C9 (250 MHz) | — |
| Temperature Grade | Industrial (0C to +85C) | — |
| 安裝類型 | Surface Mount (BGA) | Surface Mount |
| Configuration Scheme | SRAM-based, supports passive serial/parallel and JTAG | — |
| MSL 等級 | 3 (per JEDEC J-STD-020) | — |
| RoHS 狀態 | Compliant | [DATA_NEEDED: RoHS compliance status] |
| Series | — | APEX-20K |
| Logic Elements / Cells | — | 8,320 |
| Total RAM Bits | — | 106,496 |
| Number of Gates (typical) | — | 200,000 |
| Number of I/O | — | 382 |
| Voltage - Supply (VCCINT) | — | 1.71 V to 1.89 V |
| 封裝 / 外殼 | — | 484-BBGA (FineLine BGA) |
| Supplier Device Package | — | 484-FBGA (23x23 mm) |
| 工作溫度 | — | 0C to +85C (commercial grade) |
| Number of PLLs | — | 4 |
| Embedded Array Blocks (EABs) | — | Configurable as RAM/ROM/FIFO |
| Programmable Logic Blocks | — | APEX LAB architecture |
| MultiVolt I/O Support | — | 1.8V / 2.5V / 3.3V / 5V |
| Configuration Method | — | SRAM-based, in-system reconfigurable |
| 生命週期狀態 | — | Obsolete (Altera/Intel APEX-20K family EOL) |