EP20K200CF484I9N vs EP20K200CF484C9N Ikinahambing
Detalyadong pagkakahiwalay na pagkakahambing ng EP20K200CF484I9N sa pamamagitan ng Altera at EP20K200CF484C9N sa pamamagitan ng Altera. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.
Pagsanggunian na paghahambing
| Parametro | EP20K200CF484I9N | EP20K200CF484C9N |
|---|---|---|
| Brand | Altera | Altera |
| Kategorya | FPGA & CPLD | FPGA & CPLD |
| Katayuan ng Lifecycle | NRND | Obsolete |
| Family | APEX 20KC | APEX 20KC |
| Logic Elements / Cells | 8,320 | — |
| Maximum Gates | 200,000 | — |
| Maximum Internal Frequency | 250 MHz | — |
| Process Technology | 0.15 µm CMOS | 0.15 um CMOS |
| Core Supply Voltage | 1.8 V nominal (1.71 V to 1.89 V) | — |
| Packhaging | 484-pin FBGA (PBGA484), 1.0 mm pitch | 484-pin FineLine BGA (FBGA) |
| User I/O Count | 376 (368 user I/O + 4 dedicated inputs) | — |
| Speed Grade | I9 (industrial, highest-performance bin) | C9 (250 MHz) |
| Temperature na Operasyon | [DATA_NEEDED: industrial temperature range -40C to +85C assumed for I-grade] | — |
| Programmable I/O Standards | LVTTL, LVCMOS, PCI | — |
| Configuration Interface | JTAG IEEE 1149.1, ByteBlaster/BitBlaster serial | — |
| On-chip Memory | Embedded System Blocks (ESBs) for distributed RAM/ROM | — |
| Lead-Free (Pb-free) | Yes (N suffix) | — |
| Tindminan RoHS | Compliant | Compliant |
| Device Type | — | FPGA (Field-Programmable Gate Array) |
| Typical Gates | — | 200,000 |
| Logic Elements | — | 8,320 |
| Embedded System Block (ESB) Bits | — | 106,496 |
| Maximum User I/O | — | 376 |
| Maksimum na Taktiko ng Oras | — | 250 MHz |
| Core Supply Voltage (VCCINT) | — | 1.8 V |
| I/O Supply Voltage (VCCIO) | — | 3.3 V / 2.5 V / 1.8 V / 1.5 V (MultiVolt) |
| Temperature Grade | — | Industrial (0C to +85C) |
| Uri ng Pagpapasok | — | Surface Mount (BGA) |
| Configuration Scheme | — | SRAM-based, supports passive serial/parallel and JTAG |
| Level ng MSL | — | 3 (per JEDEC J-STD-020) |