EP20K200RC208-2 vs EP20K200RC208-1 Ikinahambing
Detalyadong pagkakahiwalay na pagkakahambing ng EP20K200RC208-2 sa pamamagitan ng Altera at EP20K200RC208-1 sa pamamagitan ng Intel. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.
Intel
EP20K200RC208-1 - APEX 20K 200K Gates FPGA, 208-Pin RQFP | Intel / Altera
EP20K200RC208-1 ⚠ Huling PagbiliPagsanggunian na paghahambing
| Parametro | EP20K200RC208-2 | EP20K200RC208-1 |
|---|---|---|
| Brand | Altera | Intel |
| Kategorya | FPGA & CPLD | FPGA & CPLD |
| Katayuan ng Lifecycle | NRND | Huling Pagbili |
| Series | APEX-20K | APEX 20K (200K gates) |
| Family | APEX-20K MultiCore FPGA | APEX-20K |
| Logic Elements (LEs) | 8320 | — |
| System Gates | 200,000 (typical) | 200,000 |
| Embedded Memory (bits) | 106,496 | 106,496 |
| Maximum User I/O | 144 | 144 |
| Packhaging | 208-BQFP / 208-RQFP with Exposed Pad | 208-BFQFP (RQFP) with Exposed Pad, 28×28 mm |
| Bilang ng Pin | 208 | — |
| Speed Grade | -2 (mid-speed, industrial) | — |
| Temperature na Operasyon | -40C to +85C (industrial) | Industrial range |
| Supply Voltage (Core) | [DATA_NEEDED: core VCC] | — |
| Supply Voltage (I/O) | 3.3 V (multi-standard I/O) | — |
| Configuration Interface | JTAG (IEEE 1149.1) + Altera legacy scheme | Passive Serial, Passive Parallel, JTAG (IEEE 1149.1) |
| Process Technology | [DATA_NEEDED: process node] | 0.22 µm CMOS |
| Uri ng Pagpapasok | Surface Mount | Surface Mount |
| Level ng MSL | [DATA_NEEDED: MSL rating] | [DATA_NEEDED: MSL Level] |
| Tindminan RoHS | [DATA_NEEDED: RoHS compliance] | unknown |
| Lead-Free | [DATA_NEEDED: lead-free status] | — |
| Logic Elements / Cells | — | 8,320 |
| Number of PLLs | — | 4 |
| Core Supply Voltage | — | 2.5 V |
| I/O Standard Support | — | LVTTL, LVCMOS, 2.5 V/3.3 V PCI, 1.8 V LVDS |
| Maximum Internal Frequency | — | 250 MHz |