EP20K30EFC324-1X vs EP20K100EFC324-1N Ikinahambing
Detalyadong pagkakahiwalay na pagkakahambing ng EP20K30EFC324-1X sa pamamagitan ng Intel at EP20K100EFC324-1N sa pamamagitan ng Altera. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.
Intel
EP20K30EFC324-1X - APEX 20KE FPGA, 30K Gates, 324-BGA | Intel / Altera
EP20K30EFC324-1X ObsoletePagsanggunian na paghahambing
| Parametro | EP20K30EFC324-1X | EP20K100EFC324-1N |
|---|---|---|
| Brand | Intel | Altera |
| Kategorya | FPGA & CPLD | FPGA & CPLD |
| Katayuan ng Lifecycle | Obsolete | Obsolete |
| Series | APEX 20KE | — |
| Family | APEX-20K® (MultiCore™ architecture) | APEX-20KE |
| Typical Gate Count | 30,000 gates | — |
| Logic Elements (LEs) | 1,200 | 4160 |
| Embedded Memory (RAM bits) | 24,576 | — |
| Maximum User I/O | 128 | 246 |
| Dedicated Inputs | 4 | — |
| Core Supply Voltage | 1.71 V to 1.89 V (1.8 V nominal) | — |
| I/O Standard Support | LVDS, LVTTL, LVCMOS, PCI, SSTL | LVDS, SSTL, HSTL, LVTTL, LVCMOS |
| Logic Delay (tPD) | 1.91 ns | — |
| Maksimum na Taktiko ng Oras | 909 MHz (internal), 160 MHz (I/O per partstack summary) | — |
| Process Technology | 0.22 µm CMOS | 0.15 µm all-layer copper CMOS |
| Packhaging | 324-ball FBGA (FineLine BGA), 19x19 mm | 324-BGA (FineLine BGA) |
| Uri ng Pagpapasok | Surface Mount | — |
| Configuration Method | Passive Serial, JTAG, Fast Passive Parallel | — |
| PLLs | 4 | — |
| Tindminan RoHS | Compliant | — |
| Operating Temperature Grade | Commercial (0 °C to +85 °C) per package suffix interpretation; industrial on -1X grade [DATA_NEEDED: exact Tj range] | — |
| Device Type | — | FPGA (Field Programmable Gate Array) |
| Typical Gates | — | 100,000 |
| Embedded System Blocks (ESBs) | — | 53248 bits |
| Temperature na Operasyon | — | 0 C to 85 C |
| Propagation Delay | — | 1.6 ns |
| Internal Operating Frequency | — | 250 MHz |
| Core Voltage | — | 1.8 V |
| JTAG Support | — | IEEE 1149.1 boundary-scan |
| Programming Technology | — | SRAM-based (volatile, requires configuration device) |
| MultiVolt I/O | — | 1.8 V core with 3.3 V / 5.0 V I/O support |