EP20K30EFC324-1X vs EP20K100EFC324-1N 比較

詳細並排比較 EP20K30EFC324-1X 由 Intel 與 EP20K100EFC324-1N 由 Altera. 比較關鍵規格、電氣參數、封裝、生命週期狀態、價格與供貨情況,以找出最符合您設計需求的元件。

規格比較

參數 EP20K30EFC324-1X EP20K100EFC324-1N
品牌 Intel Altera
類別 FPGA & CPLD FPGA & CPLD
生命週期狀態 Obsolete Obsolete
Series APEX 20KE —
Family APEX-20K® (MultiCore™ architecture) APEX-20KE
Typical Gate Count 30,000 gates —
Logic Elements (LEs) 1,200 4160
Embedded Memory (RAM bits) 24,576 —
Maximum User I/O 128 246
Dedicated Inputs 4 —
Core Supply Voltage 1.71 V to 1.89 V (1.8 V nominal) —
I/O Standard Support LVDS, LVTTL, LVCMOS, PCI, SSTL LVDS, SSTL, HSTL, LVTTL, LVCMOS
Logic Delay (tPD) 1.91 ns —
最大時脈頻率 909 MHz (internal), 160 MHz (I/O per partstack summary) —
Process Technology 0.22 µm CMOS 0.15 µm all-layer copper CMOS
封裝 324-ball FBGA (FineLine BGA), 19x19 mm 324-BGA (FineLine BGA)
安裝類型 Surface Mount —
Configuration Method Passive Serial, JTAG, Fast Passive Parallel —
PLLs 4 —
RoHS 狀態 Compliant —
Operating Temperature Grade Commercial (0 °C to +85 °C) per package suffix interpretation; industrial on -1X grade [DATA_NEEDED: exact Tj range] —
Device Type — FPGA (Field Programmable Gate Array)
Typical Gates — 100,000
Embedded System Blocks (ESBs) — 53248 bits
工作溫度 — 0 C to 85 C
Propagation Delay — 1.6 ns
Internal Operating Frequency — 250 MHz
Core Voltage — 1.8 V
JTAG Support — IEEE 1149.1 boundary-scan
Programming Technology — SRAM-based (volatile, requires configuration device)
MultiVolt I/O — 1.8 V core with 3.3 V / 5.0 V I/O support

資料表與資源

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