EP20K400CB652C7ES vs EP20K400CB652I7 Ikinahambing

Detalyadong pagkakahiwalay na pagkakahambing ng EP20K400CB652C7ES sa pamamagitan ng Altera at EP20K400CB652I7 sa pamamagitan ng Altera. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.

Altera
EP20K400CB652C7ES EP20K400CB652C7ES - APEX 20KC 400K Gates FPGA | Altera

EP20K400CB652C7ES - APEX 20KC 400K Gates FPGA | Altera

EP20K400CB652C7ES Obsolete

Pagsanggunian na paghahambing

Parametro EP20K400CB652C7ES EP20K400CB652I7
Brand Altera Altera
Kategorya FPGA & CPLD FPGA & CPLD
Katayuan ng Lifecycle Obsolete Obsolete
Series APEX 20KC —
Family FPGA APEX 20KC APEX 20KC
System Gates 400,000 —
Logic Cells 16,640 —
Number of Inputs 488 —
Number of I/O Lines 484 —
Bilang ng Outputs 484 —
Propagation Delay 1.4 ns —
Maksimum na Taktiko ng Oras 1666.6 MHz —
Internal Performance 375.94 MHz —
Process Technology 0.15 µm 0.15 µm CMOS
Core Supply Voltage 1.8 V 1.8 V
Package Type BGA (S-PBGA-B652) —
Number of Terminals 652 —
Package Body Material Plastic / Epoxy —
Surface Mount Yes —
Speed Grade C7 7
Temperature na Operasyon [DATA_NEEDED: Operating temperature] —
Tindminan RoHS [DATA_NEEDED: RoHS] Non-compliant (JESD-609 e0, contains lead)
Device Family — Field-Programmable Gate Array (FPGA)
Typical Gates — 400,000
Logic Elements (LEs) — 16,640
Maximum Operating Frequency — 375.94 MHz
I/O Supply Voltage — 1.8 V / 3.3 V
Packhaging — BGA-652 (652-ball)
Package Code (JESD-30) — S-PBGA-B652
Terminal Form — Ball
Package Shape — Square
Maximum User I/O Pins — [DATA_NEEDED: max user I/O]
Embedded Memory — Embedded System Blocks (ESB) - dual-port RAM / FIFO / CAM
Configuration Method — SRAM + JTAG (ISP)
Temperature Grade — Industrial (-40 °C to +100 °C)
Manufacturer Status — Obsolete (Intel/Altera legacy FPGA)

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