EP20K400CB652C7ES vs EP20K400CB652I7 比較

詳細並排比較 EP20K400CB652C7ES 由 Altera 與 EP20K400CB652I7 由 Altera. 比較關鍵規格、電氣參數、封裝、生命週期狀態、價格與供貨情況,以找出最符合您設計需求的元件。

Altera
EP20K400CB652C7ES EP20K400CB652C7ES - APEX 20KC 400K Gates FPGA | Altera

EP20K400CB652C7ES - APEX 20KC 400K Gates FPGA | Altera

EP20K400CB652C7ES Obsolete

規格比較

參數 EP20K400CB652C7ES EP20K400CB652I7
品牌 Altera Altera
類別 FPGA & CPLD FPGA & CPLD
生命週期狀態 Obsolete Obsolete
Series APEX 20KC —
Family FPGA APEX 20KC APEX 20KC
System Gates 400,000 —
Logic Cells 16,640 —
Number of Inputs 488 —
Number of I/O Lines 484 —
輸出數量 484 —
Propagation Delay 1.4 ns —
最大時脈頻率 1666.6 MHz —
Internal Performance 375.94 MHz —
Process Technology 0.15 µm 0.15 µm CMOS
Core Supply Voltage 1.8 V 1.8 V
Package Type BGA (S-PBGA-B652) —
Number of Terminals 652 —
Package Body Material Plastic / Epoxy —
Surface Mount Yes —
Speed Grade C7 7
工作溫度 [DATA_NEEDED: Operating temperature] —
RoHS 狀態 [DATA_NEEDED: RoHS] Non-compliant (JESD-609 e0, contains lead)
Device Family — Field-Programmable Gate Array (FPGA)
Typical Gates — 400,000
Logic Elements (LEs) — 16,640
Maximum Operating Frequency — 375.94 MHz
I/O Supply Voltage — 1.8 V / 3.3 V
封裝 — BGA-652 (652-ball)
Package Code (JESD-30) — S-PBGA-B652
Terminal Form — Ball
Package Shape — Square
Maximum User I/O Pins — [DATA_NEEDED: max user I/O]
Embedded Memory — Embedded System Blocks (ESB) - dual-port RAM / FIFO / CAM
Configuration Method — SRAM + JTAG (ISP)
Temperature Grade — Industrial (-40 °C to +100 °C)
Manufacturer Status — Obsolete (Intel/Altera legacy FPGA)

資料表與資源

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