EP20K400CB652I7 vs EP20K400CB652C9ES Ikinahambing
Detalyadong pagkakahiwalay na pagkakahambing ng EP20K400CB652I7 sa pamamagitan ng Altera at EP20K400CB652C9ES sa pamamagitan ng Intel. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.
Pagsanggunian na paghahambing
| Parametro | EP20K400CB652I7 | EP20K400CB652C9ES |
|---|---|---|
| Brand | Altera | Intel |
| Kategorya | FPGA & CPLD | FPGA & CPLD |
| Katayuan ng Lifecycle | Obsolete | NRND |
| Family | APEX 20KC | APEX 20KC |
| Device Family | Field-Programmable Gate Array (FPGA) | — |
| Typical Gates | 400,000 | — |
| Logic Elements (LEs) | 16,640 | — |
| Maximum Operating Frequency | 375.94 MHz | 250 MHz |
| Process Technology | 0.15 µm CMOS | 0.15 µm CMOS |
| Core Supply Voltage | 1.8 V | — |
| I/O Supply Voltage | 1.8 V / 3.3 V | — |
| Packhaging | BGA-652 (652-ball) | — |
| Package Code (JESD-30) | S-PBGA-B652 | — |
| Terminal Form | Ball | — |
| Package Shape | Square | — |
| Maximum User I/O Pins | [DATA_NEEDED: max user I/O] | — |
| Embedded Memory | Embedded System Blocks (ESB) - dual-port RAM / FIFO / CAM | — |
| Configuration Method | SRAM + JTAG (ISP) | — |
| Speed Grade | 7 | — |
| Temperature Grade | Industrial (-40 °C to +100 °C) | — |
| Tindminan RoHS | Non-compliant (JESD-609 e0, contains lead) | [DATA_NEEDED: RoHS status] |
| Manufacturer Status | Obsolete (Intel/Altera legacy FPGA) | — |
| Series | — | APEX 20KC |
| Logic Elements / Cells | — | 16640 |
| Total System Gates | — | 400000 |
| Embedded Memory (Bits) | — | 212992 |
| Number of User I/O | — | 488 |
| Number of LABs/CLBs | — | [DATA_NEEDED: LAB count] |
| Number of Logic Array Blocks | — | 1040 |
| Core Voltage | — | 1.8 V |
| Hanay ng Temperature na Operasyon | — | 0°C to +85°C (Commercial) |
| Uri ng Pagpapasok | — | Surface Mount |
| Packhaging / Kaso | — | 652-BGA |
| Level ng MSL | — | 3 (168 Hours) |
| Packaging | — | Tray |
| Programmability Type | — | In-system programmable (SRAM-based) |
| I/O Standards Supported | — | LVTTL, LVCMOS, PCI, LVDS, HSTL, SSTL |
| JTAG (IEEE 1149.1) | — | Yes |
| PLL | — | Yes (4-phase) |