EP20K400CF672C7 vs EP20K400CF672C-8 Ikinahambing
Detalyadong pagkakahiwalay na pagkakahambing ng EP20K400CF672C7 sa pamamagitan ng Altera at EP20K400CF672C-8 sa pamamagitan ng Altera. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.
Pagsanggunian na paghahambing
| Parametro | EP20K400CF672C7 | EP20K400CF672C-8 |
|---|---|---|
| Brand | Altera | Altera |
| Kategorya | FPGA & CPLD | FPGA & CPLD |
| Katayuan ng Lifecycle | Obsolete | Obsolete |
| Series | APEX-20KC | — |
| Family | APEX 20KC (MultiCore™) | APEX 20K |
| Logic Elements / Cells | 16,640 | — |
| System Gates | 400,000 | — |
| Embedded Memory (RAM bits) | 212,992 | — |
| Maximum User I/O | 488 | 488 |
| Number of I/O Banks | 8 | [DATA_NEEDED: number of I/O banks] |
| Packhaging | 672-BBGA (FC-FBGA, FineLine BGA) | — |
| Bilang ng Pin | 672 | — |
| Core Voltage | 1.8 V | — |
| Volte ng Pagbibigay | 2.5 V (I/O reference) | — |
| Process Technology | 0.15 µm CMOS | 0.15 µm all-layer copper CMOS |
| Propagation Delay (tPD) | 2.5 ns | — |
| Maximum Internal Frequency | 375.94 MHz | — |
| Temperature na Operasyon | 0 °C to +85 °C (Commercial, C-grade) | — |
| PLL Count | 4 | — |
| Speed Grade | -7 | -8 |
| Uri ng Pagpapasok | Surface Mount (BGA) | Surface Mount (BGA) |
| Tindminan RoHS | Non-compliant (legacy product) | [DATA_NEEDED: RoHS compliance] |
| Lead-Free | Contains lead (legacy BGA finish) | — |
| Logic Elements | — | 16,640 |
| Typical Gates | — | 400,000 |
| Macros | — | 1,664 |
| Package Type | — | PBGA-672 (FineLine BGA, 27 x 27 mm, 1.0 mm pitch) |
| Core Voltage (VCCINT) | — | 1.8 V nominal (1.71 V to 1.89 V) |
| I/O Voltage (VCCIO) | — | [DATA_NEEDED: VCCIO options] |
| Pin-to-Pin Delay (tPD) | — | 1.78 ns (speed grade -8) |
| Temperature Grade (C) | — | Commercial, 0 °C to 85 °C |
| Embedded Memory Type | — | ESB (RAM / ROM / CAM) |
| Configuration Interface | — | JTAG (IEEE 1149.1), Passive Serial, Passive Parallel |
| JTAG Support | — | Yes (IEEE 1149.1 boundary-scan) |
| Level ng MSL | — | [DATA_NEEDED: MSL level] |