EP20K400CF672C7 vs EP20K400CF672C7N Ikinahambing
Detalyadong pagkakahiwalay na pagkakahambing ng EP20K400CF672C7 sa pamamagitan ng Altera at EP20K400CF672C7N sa pamamagitan ng Altera. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.
Pagsanggunian na paghahambing
| Parametro | EP20K400CF672C7 | EP20K400CF672C7N |
|---|---|---|
| Brand | Altera | Altera |
| Kategorya | FPGA & CPLD | FPGA & CPLD |
| Katayuan ng Lifecycle | Obsolete | Obsolete |
| Series | APEX-20KC | — |
| Family | APEX 20KC (MultiCore™) | APEX 20KC |
| Logic Elements / Cells | 16,640 | — |
| System Gates | 400,000 | — |
| Embedded Memory (RAM bits) | 212,992 | — |
| Maximum User I/O | 488 | 488 |
| Number of I/O Banks | 8 | — |
| Packhaging | 672-BBGA (FC-FBGA, FineLine BGA) | 672-ball FineLine BGA (FC-FBGA / BBGA) |
| Bilang ng Pin | 672 | — |
| Core Voltage | 1.8 V | — |
| Volte ng Pagbibigay | 2.5 V (I/O reference) | — |
| Process Technology | 0.15 µm CMOS | 0.18-micron CMOS, all-layer copper interconnect |
| Propagation Delay (tPD) | 2.5 ns | — |
| Maximum Internal Frequency | 375.94 MHz | — |
| Temperature na Operasyon | 0 °C to +85 °C (Commercial, C-grade) | 0 C to 85 C (Commercial) |
| PLL Count | 4 | — |
| Speed Grade | -7 | — |
| Uri ng Pagpapasok | Surface Mount (BGA) | Surface Mount (BGA) |
| Tindminan RoHS | Non-compliant (legacy product) | [DATA_NEEDED: RoHS status not in provided data] |
| Lead-Free | Contains lead (legacy BGA finish) | — |
| Maximum System Gates | — | 1,052,000 |
| Typical Gates | — | 400,000 |
| Logic Elements (LEs) | — | 16,640 |
| Embedded Memory | — | 488 Kbits |
| User I/O (per catalog) | — | 480 / 502 (per source) |
| Core Voltage (VCCINT) | — | 1.8 V |
| I/O Voltage (VCCIO) | — | 3.3 V / 2.5 V banked |
| Propagation Delay | — | 2.5 ns (catalog) / 1.48 ns (some catalog) |
| Maximum Frequency | — | 375.94 MHz (internal) |
| Level ng MSL | — | 3 (per JEDEC J-STD-020) |
| Configuration Modes | — | PS, PPS, JTAG |