EP20K400CF672C7GA vs EP20K400CF672C-8 Ikinahambing
Detalyadong pagkakahiwalay na pagkakahambing ng EP20K400CF672C7GA sa pamamagitan ng Intel at EP20K400CF672C-8 sa pamamagitan ng Altera. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.
Pagsanggunian na paghahambing
| Parametro | EP20K400CF672C7GA | EP20K400CF672C-8 |
|---|---|---|
| Brand | Intel | Altera |
| Kategorya | FPGA & CPLD | FPGA & CPLD |
| Katayuan ng Lifecycle | Obsolete | Obsolete |
| Series | APEX-20KC | — |
| Logic Elements | 212992 | 16,640 |
| Number of LABs/CLBs | 488 | — |
| Total RAM Bits | 16640 | — |
| Number of I/O | [DATA_NEEDED: max user I/O count] | — |
| Number of Gates | 400000 | — |
| Voltage - Supply | 2.5 V core | — |
| Uri ng Pagpapasok | Surface Mount | Surface Mount (BGA) |
| Packhaging / Kaso | 672-BBGA (FineLine BGA) | — |
| Temperature na Operasyon | 0C to +85C | — |
| Speed Grade | C7 (7 ns pin-to-pin) | -8 |
| Process Technology | 0.18 um CMOS | 0.15 µm all-layer copper CMOS |
| Programming Method | In-System Programmable (ISP) via JTAG | — |
| Tindminan RoHS | [DATA_NEEDED: RoHS compliance] | [DATA_NEEDED: RoHS compliance] |
| Lead Free | [DATA_NEEDED: lead-free status] | — |
| Level ng MSL | [DATA_NEEDED: moisture sensitivity level] | [DATA_NEEDED: MSL level] |
| Family | — | APEX 20K |
| Typical Gates | — | 400,000 |
| Macros | — | 1,664 |
| Maximum User I/O | — | 488 |
| Number of I/O Banks | — | [DATA_NEEDED: number of I/O banks] |
| Package Type | — | PBGA-672 (FineLine BGA, 27 x 27 mm, 1.0 mm pitch) |
| Core Voltage (VCCINT) | — | 1.8 V nominal (1.71 V to 1.89 V) |
| I/O Voltage (VCCIO) | — | [DATA_NEEDED: VCCIO options] |
| Pin-to-Pin Delay (tPD) | — | 1.78 ns (speed grade -8) |
| Temperature Grade (C) | — | Commercial, 0 °C to 85 °C |
| Embedded Memory Type | — | ESB (RAM / ROM / CAM) |
| Configuration Interface | — | JTAG (IEEE 1149.1), Passive Serial, Passive Parallel |
| JTAG Support | — | Yes (IEEE 1149.1 boundary-scan) |