EP20K400FI672-3 vs EP20K400FI672-3V Ikinahambing

Detalyadong pagkakahiwalay na pagkakahambing ng EP20K400FI672-3 sa pamamagitan ng Altera at EP20K400FI672-3V sa pamamagitan ng Intel. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.

Pagsanggunian na paghahambing

Parametro EP20K400FI672-3 EP20K400FI672-3V
Brand Altera Intel
Kategorya FPGA & CPLD FPGA & CPLD
Katayuan ng Lifecycle Obsolete Obsolete
Family APEX 20K APEX 20K (EP20K400)
Series EP20K400 —
Logic Elements 16640 16,640
Total Gates up to 400000 —
Embedded RAM 212992 bits —
Maximum User I/O 502 502
Dedicated Inputs 6 6
Propagation Delay 3.6 ns —
Maksimum na Taktiko ng Oras 833 MHz 714.2 MHz
Supply Voltage (Nominal) 2.5 V —
Supply Voltage Range 2.375 V to 2.625 V —
Process Technology CMOS 0.18 µm CMOS, 4 metal layers
Package Type PBGA (Plastic BGA) —
Package Code S-PBGA-B672 —
Terminal Count 672 —
Terminal Pitch 1.000 mm —
Package Shape Square BGA —
Uri ng Pagpapasok Surface Mount Surface Mount
Configuration Interface JTAG (IEEE 1149.1) —
Temperature na Operasyon [DATA_NEEDED: operating temperature range] -40 °C to +85 °C (industrial)
Level ng MSL 3 [DATA_NEEDED: MSL rating]
Peak Reflow Temperature 220 C —
Maximum Gates — 400,000
Typical Gates — [DATA_NEEDED: typical gates value]
Embedded Memory (bits) — 212,992
Total User I/O + Dedicated Inputs — 496 + 6 (variant dependent)
Speed Grade — -3 (faster)
Core Voltage (VCCINT) — 2.5 V nominal (2.375 V to 2.625 V)
Packhaging — 672-ball FineLine BGA (BBGA), 1.0 mm pitch
Programmable via JTAG — Yes (IEEE 1149.1)
Supported I/O Standards — LVCMOS, LVTTL, SSTL, GTL+, HSTL
Configuration Modes — JTAG, passive serial, passive parallel
Tindminan RoHS — [DATA_NEEDED: RoHS status]

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