EP20K400FI672-3V vs EP20K400FI672-3 Ikinahambing
Detalyadong pagkakahiwalay na pagkakahambing ng EP20K400FI672-3V sa pamamagitan ng Intel at EP20K400FI672-3 sa pamamagitan ng Altera. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.
Pagsanggunian na paghahambing
| Parametro | EP20K400FI672-3V | EP20K400FI672-3 |
|---|---|---|
| Brand | Intel | Altera |
| Kategorya | FPGA & CPLD | FPGA & CPLD |
| Katayuan ng Lifecycle | Obsolete | Obsolete |
| Family | APEX 20K (EP20K400) | APEX 20K |
| Logic Elements | 16,640 | 16640 |
| Maximum Gates | 400,000 | — |
| Typical Gates | [DATA_NEEDED: typical gates value] | — |
| Embedded Memory (bits) | 212,992 | — |
| Maximum User I/O | 502 | 502 |
| Dedicated Inputs | 6 | 6 |
| Total User I/O + Dedicated Inputs | 496 + 6 (variant dependent) | — |
| Maksimum na Taktiko ng Oras | 714.2 MHz | 833 MHz |
| Speed Grade | -3 (faster) | — |
| Core Voltage (VCCINT) | 2.5 V nominal (2.375 V to 2.625 V) | — |
| Process Technology | 0.18 µm CMOS, 4 metal layers | CMOS |
| Packhaging | 672-ball FineLine BGA (BBGA), 1.0 mm pitch | — |
| Uri ng Pagpapasok | Surface Mount | Surface Mount |
| Programmable via JTAG | Yes (IEEE 1149.1) | — |
| Supported I/O Standards | LVCMOS, LVTTL, SSTL, GTL+, HSTL | — |
| Configuration Modes | JTAG, passive serial, passive parallel | — |
| Tindminan RoHS | [DATA_NEEDED: RoHS status] | — |
| Temperature na Operasyon | -40 °C to +85 °C (industrial) | [DATA_NEEDED: operating temperature range] |
| Level ng MSL | [DATA_NEEDED: MSL rating] | 3 |
| Series | — | EP20K400 |
| Total Gates | — | up to 400000 |
| Embedded RAM | — | 212992 bits |
| Propagation Delay | — | 3.6 ns |
| Supply Voltage (Nominal) | — | 2.5 V |
| Supply Voltage Range | — | 2.375 V to 2.625 V |
| Package Type | — | PBGA (Plastic BGA) |
| Package Code | — | S-PBGA-B672 |
| Terminal Count | — | 672 |
| Terminal Pitch | — | 1.000 mm |
| Package Shape | — | Square BGA |
| Configuration Interface | — | JTAG (IEEE 1149.1) |
| Peak Reflow Temperature | — | 220 C |