EP20K400GC655-2N vs EP20K400GC655-2V Ikinahambing
Detalyadong pagkakahiwalay na pagkakahambing ng EP20K400GC655-2N sa pamamagitan ng Altera at EP20K400GC655-2V sa pamamagitan ng Altera. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.
Altera
EP20K400GC655-2V - 400K Gate APEX-20KC FPGA 655-CPGA | Altera
EP20K400GC655-2V ⚠ Huling PagbiliPagsanggunian na paghahambing
| Parametro | EP20K400GC655-2N | EP20K400GC655-2V |
|---|---|---|
| Brand | Altera | Altera |
| Kategorya | FPGA & CPLD | FPGA & CPLD |
| Katayuan ng Lifecycle | Obsolete | Huling Pagbili |
| Family | APEX 20KC | APEX 20KC (1.8 V, LVDS) |
| Number of Logic Elements | 16640 | — |
| Number of Logic Cells | 16640 | — |
| Total System Gates | 400000 | — |
| Total RAM Bits | 212992 | 212,992 |
| Number of I/O | [DATA_NEEDED: I/O count] | [DATA_NEEDED: I/O count] |
| Number of LABs/CLBs | [DATA_NEEDED: LAB count] | — |
| Core Voltage (VCCINT) | 1.71 V to 1.89 V | 2.375 V to 2.625 V (nominal 2.5 V) |
| I/O Voltage (VCCIO) | 2.5 V (LVDS-capable) | — |
| Process Technology | 0.22 µm CMOS | CMOS, 0.18 um |
| Maximum Operating Frequency | 200 MHz | — |
| Propagation Delay (Tpd) | 3.1 ns | — |
| Packhaging / Kaso | 655-BCPGA (Ceramic Pin Grid Array) | — |
| Supplier Device Package | 655-CPGA, 62.48 x 62.48 mm | — |
| Temperature na Operasyon | Industrial (per Altera part-number -N suffix) | [DATA_NEEDED: temperature grade] |
| Uri ng Pagpapasok | Through-Hole (CPGA, socket-compatible) | Through-hole (CPGA) |
| LVDS Support | Yes | Yes |
| Architecture | MultiCore (LUT + product-term + embedded memory) | MultiCore (LUT + product-term + embedded memory) |
| Configuration Method | JTAG / Passive Serial | — |
| Tindminan RoHS | [DATA_NEEDED: RoHS status] | unknown |
| Level ng MSL | [DATA_NEEDED: MSL level] | — |
| Series | — | APEX-20KC |
| Logic Elements | — | 16,640 |
| System Gates | — | ~400,000 (typical marketing figure) |
| Propagation Delay | — | 3.000 ns |
| Packhaging | — | 655-CPGA (62.48 x 62.48 mm) |
| Package Type | — | Ceramic Pin Grid Array, through-hole |
| Speed Grade | — | -2 |
| Lead-Free | — | unknown |