EP20K400GC655-2V vs EP20K400GC655-2N Ikinahambing
Detalyadong pagkakahiwalay na pagkakahambing ng EP20K400GC655-2V sa pamamagitan ng Altera at EP20K400GC655-2N sa pamamagitan ng Altera. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.
Altera
EP20K400GC655-2V - 400K Gate APEX-20KC FPGA 655-CPGA | Altera
EP20K400GC655-2V ⚠ Huling PagbiliPagsanggunian na paghahambing
| Parametro | EP20K400GC655-2V | EP20K400GC655-2N |
|---|---|---|
| Brand | Altera | Altera |
| Kategorya | FPGA & CPLD | FPGA & CPLD |
| Katayuan ng Lifecycle | Huling Pagbili | Obsolete |
| Series | APEX-20KC | — |
| Family | APEX 20KC (1.8 V, LVDS) | APEX 20KC |
| Logic Elements | 16,640 | — |
| Total RAM Bits | 212,992 | 212992 |
| System Gates | ~400,000 (typical marketing figure) | — |
| Number of I/O | [DATA_NEEDED: I/O count] | [DATA_NEEDED: I/O count] |
| Core Voltage (VCCINT) | 2.375 V to 2.625 V (nominal 2.5 V) | 1.71 V to 1.89 V |
| Propagation Delay | 3.000 ns | — |
| Process Technology | CMOS, 0.18 um | 0.22 µm CMOS |
| LVDS Support | Yes | Yes |
| Packhaging | 655-CPGA (62.48 x 62.48 mm) | — |
| Package Type | Ceramic Pin Grid Array, through-hole | — |
| Uri ng Pagpapasok | Through-hole (CPGA) | Through-Hole (CPGA, socket-compatible) |
| Speed Grade | -2 | — |
| Temperature na Operasyon | [DATA_NEEDED: temperature grade] | Industrial (per Altera part-number -N suffix) |
| Tindminan RoHS | unknown | [DATA_NEEDED: RoHS status] |
| Lead-Free | unknown | — |
| Architecture | MultiCore (LUT + product-term + embedded memory) | MultiCore (LUT + product-term + embedded memory) |
| Number of Logic Elements | — | 16640 |
| Number of Logic Cells | — | 16640 |
| Total System Gates | — | 400000 |
| Number of LABs/CLBs | — | [DATA_NEEDED: LAB count] |
| I/O Voltage (VCCIO) | — | 2.5 V (LVDS-capable) |
| Maximum Operating Frequency | — | 200 MHz |
| Propagation Delay (Tpd) | — | 3.1 ns |
| Packhaging / Kaso | — | 655-BCPGA (Ceramic Pin Grid Array) |
| Supplier Device Package | — | 655-CPGA, 62.48 x 62.48 mm |
| Configuration Method | — | JTAG / Passive Serial |
| Level ng MSL | — | [DATA_NEEDED: MSL level] |