EP20K400GC655-3 vs EP20K400GC655-3X Ikinahambing

Detalyadong pagkakahiwalay na pagkakahambing ng EP20K400GC655-3 sa pamamagitan ng Intel at EP20K400GC655-3X sa pamamagitan ng Altera. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.

Intel
EP20K400GC655-3 EP20K400GC655-3 - 400K Gate APEX-20KC FPGA 655-BCPGA | Intel

EP20K400GC655-3 - 400K Gate APEX-20KC FPGA 655-BCPGA | Intel

EP20K400GC655-3 ⚠ Huling Pagbili

Pagsanggunian na paghahambing

Parametro EP20K400GC655-3 EP20K400GC655-3X
Brand Intel Altera
Kategorya FPGA & CPLD FPGA & CPLD
Katayuan ng Lifecycle Huling Pagbili Obsolete
Series APEX-20KC APEX-20KC
Family APEX 20K APEX 20K (MultiCore architecture, LUT + product-term + embedded memory)
Manufacturer Intel (formerly Altera) Altera (now Intel FPGA)
Logic Elements 16640 —
Total RAM Bits 212992 212,992 bits
Number of Gates 400000 —
Supply Voltage - Core 1.71 V to 1.89 V (1.8 V nominal) —
I/O Voltage Tolerance MultiVolt I/O: 1.8 V / 2.5 V / 3.3 V / 5 V —
Temperature na Operasyon -40C to +85C (industrial) [DATA_NEEDED: operating temperature range]
Maximum Frequency 167 MHz (per FPGAkey) —
Process Technology 0.22 um CMOS 0.22 µm CMOS
Packhaging / Kaso 655-BCPGA 655-BCPGA (CPGA655, 62.48 x 62.48 mm)
Supplier Device Package 655-CPGA (62.48 x 62.48 mm) —
Speed Grade -3 (slowest grade in family) -3 (fastest)
Propagation Delay (tPD) 3.6 ns (per Microchip USA listing) —
JTAG Support IEEE 1149.1 Boundary-Scan —
Configuration Modes Passive Serial, Passive Parallel Sync/Async, Active Serial —
Tindminan RoHS [DATA_NEEDED: rohs status] [DATA_NEEDED: RoHS status - ceramic CPGA historically non-RoHS]
Logic Elements / Cells — 16,640
System Gates — 400,000
Maximum Internal Frequency — 167 MHz (speed grade -3)
Core Supply Voltage (VCCINT) — 1.71 V to 1.89 V
I/O Supply Voltage (VCCIO) — 2.5 V (LVDS support per APEX 20KE datasheet)
Uri ng Pagpapasok — Through-Hole (CPGA, ceramic)
Suffix Code — -X (extended / ceramic CPGA variant)
I/O Count — [DATA_NEEDED: max user I/O]
JTAG / Boundary Scan — IEEE 1149.1 (per APEX 20K family)

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